Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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This mode can be used when the minimum period of time between two successive trigger events is greater than
the startup period of Analog-Digital converter (see the AFEC electrical characteristics in the product datasheet).

When a start conversion request occurs, the AFEC is automatically activated. As the analog cell requires a start-up
time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are
complete, the AFEC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into
account.

A fast wake-up mode is available in the AFEC_MR as a compromise between power saving strategy and
responsiveness. Setting the FWUP bit to ‘1’ enables the fast wake-up mode. In fast wake-up mode the AFEC cell
is not fully deactivated while no conversion is requested, thereby providing less power saving but faster wake-up.

The conversion sequencer allows automatic processing with minimum processor intervention and optimized power
consumption. Conversion sequences can be performed periodically using a Timer/Counter output or the PWM
event line. 

The PDC can automatically process the periodic acquisition of several samples without any intervention of the
processor.

The sequence can be customized by programming the Sequence Channel Registers, AFEC_SEQR1 and
AFEC_SEQR2 and setting to 1 the USEQ bit of the AFEC_MR. The user can choose a specific order of channels
and can program up to 16 conversions by sequence. The user is totally free to create a personal sequence, by
writing channel numbers in AFEC_SEQR1 and AFEC_SEQR2. Not only can channel numbers be written in any
sequence, channel numbers can be repeated several times. Only enabled sequence bitfields are converted,
consequently to program a 15-conversion sequence, the user can simply put a disable in AFEC_CHSR[15], thus
disabling the 16THCH field of AFEC_SEQR2.

Note:

The reference voltage pins always remain connected in normal mode as in sleep mode.

The AFE Controller features automatic comparison functions. It compares converted values to a low threshold or a
high threshold or both, according to the CMPMODE function chosen in the Extended Mode Register
(AFEC_EMR). The comparison can be done on all channels or only on the channel specified in CMPSEL field of
AFEC_EMR. To compare all channels the CMP_ALL parameter must be set. 

Moreover a filtering option can be set by writing the number of consecutive comparison errors needed to raise the
flag. This number can be written and read in the CMPFILTER field of the AFEC_EMR.

The flag can be read on the COMPE bit of the Interrupt Status Register (AFEC_IS1R) and can trigger an interrupt.

The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (AFEC_CWR). 

Depending on the sign of the conversion (chosen by setting the SIGNMODE bit in the 

, the High Threshold and Low Threshold values must be signed or unsigned to keep consistency during

the comparison. If the conversion is signed, both thresholds must also be signed; if the conversion is unsigned,
both thresholds must be unsigned. If comparison occurs on all channels, the SIGNMODE bit must be set to
ALL_UNSIGNED or ALL_SIGNED value and thresholds must be set accordingly.

The AFEC can be used either as a single ended AFEC (DIFF bit equal to 0) or as a fully differential AFEC (DIFF bit
equal to 1) as shown in 

. By default, after a reset, the AFEC is in single ended mode. 

If ANACH is set in AFEC_MR, the AFEC can apply a different mode on each channel. Otherwise the parameters of
CH0 are applied to all channels.

The same inputs are used in single ended or differential mode.

Depending on the mode (single ended or differential), the analog multiplexer selects one or two inputs to map to a
channel. 

 below provide input mapping for both modes.