Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
586
30.3
Block Diagram
Figure 30-1.
General Clock Block Diagram
30.4
Master Clock Controller
The Master Clock Controller provides selection and division of the master clock (MCK). MCK is the clock provided
to all the peripherals. The master clock is selected from one of the clocks provided by the Clock Generator.
to all the peripherals. The master clock is selected from one of the clocks provided by the Clock Generator.
Selecting the slow clock provides a slow clock signal to the whole device. Selecting the main clock saves power
consumption of the PLL. The Master Clock Controller is made up of a clock selector and a prescaler.
consumption of the PLL. The Master Clock Controller is made up of a clock selector and a prescaler.
The master clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR.
The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3.
The PRES field in PMC_MCKR programs the prescaler.
The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3.
The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in PMC_SR. It reads 0
until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor.
This feature is useful when switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor.
This feature is useful when switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
Management
Controller
Main Clock
MAINCK
MAINCK
PLLA Clock
PLLACK
PLLACK
Control
Status
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
PLLA and
Divider/2
Divider/2
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
Embedded
32 kHz RC
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
0
1
0
1
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/3,/4,/8,
/16,/32,/64
/16,/32,/64
HCLK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
(PMC_MCKR)
Clock Controller
(PMC_PCERx) ON/OFF
(PMC_PCERx) ON/OFF
Prescaler
/1,/2,/4,/8,
/16,/32,/64
/16,/32,/64
pck[..]
ON/OFF
FCLK
SysTick
Divider
/8
SLCK
MAINCK
PLLACK
Processor Clock
Free Running Clock
Master Clock
Embedded
4/8/12 MHz
Fast
RC Oscillator
Programmable Clock Controller
(PMC_PCKx)
(PMC_PCKx)
PRES
PLLADIV2
PRES
CSS
CSS
MCK
USB FS Clock
USB_48M
Divider
/1,/2,/3,...,/16
USB Clock Controller (PMC_USB)
USBDIV
ON/OFF
Peripherals
Slow Clock
Power
XTALSEL
Clock Generator
PMC_MCKR
MOSCSEL
CKGR_MOR