Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
630
In CTR mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after
processing 1 megabyte of data. If the file to be processed is greater than 1 megabyte, this file must be split into
fragments of 1 megabyte. Prior to loading the first fragment into AES_IDATARx, AES_IVRx must be fully
programmed with the initial counter value. For any fragment, after the transfer is completed and prior to
transferring the next fragment, AES_IVRx must be programmed with the appropriate counter value.
processing 1 megabyte of data. If the file to be processed is greater than 1 megabyte, this file must be split into
fragments of 1 megabyte. Prior to loading the first fragment into AES_IDATARx, AES_IVRx must be fully
programmed with the initial counter value. For any fragment, after the transfer is completed and prior to
transferring the next fragment, AES_IVRx must be programmed with the appropriate counter value.
To have a sequential increment, the counter value must be programmed with the value programmed for the
previous fragment + 2exp16.
previous fragment + 2exp16.
All AES_IVRx fields must be programmed to take into account the possible carry propagation.
31.4.2 Double Input Buffer
The AES_IDATARx can be double-buffered to reduce the runtime of large files.
This mode allows writing a new message block when the previous message block is being processed. This is only
possible when DMA accesses are performed (SMOD = 0x2).
possible when DMA accesses are performed (SMOD = 0x2).
The DUALBUFF bit in the AES_MR must be set to 1 to access the double buffer.
31.4.3 Start Modes
The SMOD field in the AES_MR allows selection of the encryption (or decryption) start mode.
31.4.3.1 Manual Mode
The sequence order is as follows:
Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD.
Write the 128-bit/192-bit/256-bit key in the AES_KEYWRx.
Write the initialization vector (or counter) in the AES_IVRx.
Note:
The AES_IVRx concern all modes except ECB.
Set the bit DATRDY (Data Ready) in the AES Interrupt Enable Register (AES_IER), depending on whether
an interrupt is required or not at the end of processing.
an interrupt is required or not at the end of processing.
Write the data to be encrypted/decrypted in the authorized AES_IDATARx (See
Note:
In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing.
Note:
In 32-, 16- and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not allowed and may
lead to errors in processing.
lead to errors in processing.
Set the START bit in the AES Control Register (AES_CR) to begin the encryption or the decryption process.
Table 31-2.
Authorized Input Data Registers
Operation Mode
Input Data Registers to Write
ECB
All
CBC
All
OFB
All
128-bit CFB
All
64-bit CFB
AES_IDATAR0 and AES_IDATAR1
32-bit CFB
AES_IDATAR0
16-bit CFB
AES_IDATAR0
8-bit CFB
AES_IDATAR0
CTR
All