Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
721
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
These additional modes are:
Rising edge detection
Falling edge detection
Low-level detection
High-level detection
In order to select an additional interrupt mode:
The type of event detection (edge or level) must be selected by writing in the Edge Select register
(PIO_ESR) and Level Select register (PIO_LSR) which select, respectively, the edge and level detection.
The current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR).
(PIO_ESR) and Level Select register (PIO_LSR) which select, respectively, the edge and level detection.
The current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR).
The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the
Falling Edge/Low-Level Select register (PIO_FELLSR) and Rising Edge/High-Level Select register
(PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high-
or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible
through the Fall/Rise - Low/High Status register (PIO_FRLHSR).
Falling Edge/Low-Level Select register (PIO_FELLSR) and Rising Edge/High-Level Select register
(PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high-
or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible
through the Fall/Rise - Low/High Status register (PIO_FRLHSR).
When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status register
(PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The
interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt
controller.
(PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The
interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt
controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.