Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
830
address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after
sending the IADR) is sometimes called “repeated start” (Sr) in I
sending the IADR) is sometimes called “repeated start” (Sr) in I
2
C fully-compatible devices. See
and
for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode Register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be set to 0.
shows the abbreviations used in
and
.
Figure 36-12. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 36-13. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
10-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave
address bits in the Internal Address Register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8]
and IADR[23:16] can be used the same as in 7-bit Slave Addressing.
address bits in the Internal Address Register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8]
and IADR[23:16] can be used the same as in 7-bit Slave Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
Table 36-6.
Abbreviations
Abbreviation
Definition
S
Start
Sr
Repeated Start
P
Stop
W
Write
R
Read
A
Acknowledge
NA
Not Acknowledge
DADR
Device Address
IADR
Internal Address
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
DATA
A
P
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
P
DATA
A
A
IADR(7:0)
A
P
DATA
A
S
DADR
W
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
A
IADR(7:0)
A
S
DADR
W
DATA
NA
P
Sr
DADR
R
A
Sr
DADR
R
A
DATA
NA
P
Sr
DADR
R
A
DATA
NA
P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address