Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données

32072H–AVR32–10/2012

Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set. 

TWIS stretch on Address match error
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for
the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD
at the same time. This can cause a TWI timing violation.
Fix/Workaround
None. 

MCI_CLK features is not available on PX12, PX13 and PX40
Fix/Workaround
MCI_CLK feature is available on PA27 only. 

The busy signal of the responses R1b is not taken in account for CMD12
STOP_TRANSFER
It is not possible to know the busy status of the card during the response (R1b) for the com-
mands CMD12.
Fix/Workaround
The card busy line should be polled through the GPIO Input Value register (IVR) for com-
mands CMD12.

Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro. 

Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other errors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.