Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The user can control the oscillation frequency by writing to the Frequency Range (FRANGE) and Calibration (CALIB) bit 
groups in the 8MHz RC Oscillator Control register (OSC8M). It is not recommended to update the FRANGE and CALIB 
bits when the OSC8M is enabled. As this is in open-loop mode, the frequency will be voltage, temperature and process 
dependent. Refer to the 

 for details.

OSC8M is automatically switched off in certain sleep modes to reduce power consumption, as described in the 

.

The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-frequency clock 
with high accuracy can be used as the reference clock to get high accuracy on the output clock (CLK_DFLL48M).

The DFLL48M can be used as a source for the generic clock generators, as described in the 

After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the 
DFLL48M will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit 
group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value 
from 

 in DFLL.COARSE helps to output a frequency close to 48 MHz.

It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output frequency of the 
DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use. CLK_DFLL48M is ready to be used 
when PCLKSR.DFLLRDY is set after enabling the DFLL48M.

In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once the 
multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be correctly configured 
before closed-loop operation can be enabled. After enabling the DFLL48M, it must be configured in the following way:

1.

Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0 
(GCLK_DFLL48M_REF). Refer to 

 for details.

2.

Select the maximum step size allowed in finding the Coarse and Fine values by writing the appropriate values to 
the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and DFLL-
MUL.FSTEP) in the DFLL Multiplier register. A small step size will ensure low overshoot on the output frequency, 
but will typically result in longer lock times. A high value might give a large overshoot, but will typically provide 
faster locking. DFLLMUL.CSTEP and DFLLMUL.FSTEP should not be higher than 50% of the maximum value of 
DFLLVAL.COARSE and DFLLVAL.FINE, respectively.

3.

Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier regis-
ter. Care must be taken when choosing DFLLMUL.MUL so that the output frequency does not exceed the 
maximum frequency of the DFLL. If the target frequency is below the minimum frequency of the DFLL48M, the out-
put frequency will be equal to the DFLL minimum frequency.

4.

Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRL.MODE) in the DFLL Con-
trol register.

The frequency of CLK_DFLL48M (F

clkdfll48m

) is given by:

where F

clkdfll48mref

 is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE and 

DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet user specified 
frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency tuner as a starting point for 
Coarse. Writing DFLLVAL.COARSE to a value close to the final value before entering closed-loop mode will reduce the 
time needed to get a lock on Coarse.

clkdfll48m

clkdfll48mref

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