Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

When configured as a master (CTRLA.MODE is 0x3), if Master Slave Select Enable (CTRLB.MSSEN) is set to zero the 
_SS line can be located at any general purpose I/O pin, and must be configured as an output. When the SPI is ready for 
a data transaction, software must pull the _SS line low. If Master Slave Enable Select (CTRLB.MSSEN) is set to one, 
hardware controls the _SS line.

When writing a character to the Data register (DATA), the character will be transferred to the shift register when the shift 
register is empty. Once the contents of TxDATA have been transferred to the shift register, the Data Register Empty flag 
in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set, and a new character can be written to DATA.

As each character is shifted out from the master, another character is shifted in from the slave. If the receiver is enabled 
(CTRLA.RXEN is one), the contents of the shift register will be transferred to the two-level receive buffer. The transfer 
takes place in the same clock cycle as the last data bit is shifted in, and the Receive Complete Interrupt flag in the 
Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading 
DATA.

Bit 1
Bit 6

LSB
MSB

Mode 0

SAMPLE I
MOSI/MISO

CHANGE 0
MOSI PIN

CHANGE 0
MISO PIN

Mode 2

SS

MSB
LSB

Bit 6
Bit 1

Bit 5
Bit 2

Bit 4
Bit 3

Bit 3
Bit 4

Bit 2
Bit 5

MSB first (DORD = 0)
LSB first (DORD = 1)

Mode 1

SAMPLE I
MOSI/MISO

CHANGE 0
MOSI PIN

CHANGE 0
MISO PIN

Mode 3

SS