Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
473
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
26.6.3.2 Preloading of the Slave Shift Register
When starting a transaction, the slave will first transmit the contents of the shift register before loading new data from
DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the
last reset) or the last character in the previous transmission. Preloading can be used to preload data to the shift register
while _SS is high and eliminate sending a dummy character when starting a transaction.
DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the
last reset) or the last character in the previous transmission. Preloading can be used to preload data to the shift register
while _SS is high and eliminate sending a dummy character when starting a transaction.
In order to guarantee enough set-up time before the first SCK edge, enough time must be given between _SS going low
and the first SCK sampling edge, as shown in
and the first SCK sampling edge, as shown in
.
Preloading is enabled by setting the Slave Data Preload Enable bit in the Control B register (CTRLB.PLOADEN).
Figure 26-4. Timing Using Preloading
Only one data character written to DATA will be preloaded into the shift register while the synchronized _SS signal (see
) is high. The next character written to DATA before _SS is pulled low will be stored in DATA until transfer
begins. If the shift register is not preloaded, the current contents of the shift register will be shifted out.
26.6.3.3 Master with Several Slaves
Master with multiple slaves in parallel feature is available only when Master Slave Select Enable (CTRLB.MSSEN) is set
to zero and hardware _SS control is disabled. If the bus consists of several SPI slaves, an SPI master can use general
purpose I/O pins to control the _SS line to each of the slaves on the bus, as shown in
to zero and hardware _SS control is disabled. If the bus consists of several SPI slaves, an SPI master can use general
purpose I/O pins to control the _SS line to each of the slaves on the bus, as shown in
. In this configuration,
the single selected SPI slave will drive the tri-state MISO line.
Figure 26-5. Multiple Slaves in Parallel
An alternate configuration is shown in
. In this configuration, all n attached slaves are connected in series. A
common _SS line is provided to all slaves, enabling them simultaneously. The master must shift n characters for a
complete transaction. Depending on the Master Slave Select Enable bit (CTRLB.MSSEN), _SS line is controlled either
by hardware or by user software and normal GPIO
complete transaction. Depending on the Master Slave Select Enable bit (CTRLB.MSSEN), _SS line is controlled either
by hardware or by user software and normal GPIO
_SS
Synchronization to
system domain
MISO to SCK
setup time
Required _SS to SCK time using
PRELOADEN
_SS synchronized to
system domain
SCK
shift register
shift register
MOSI
MISO
MISO
SCK
_SS[0]
MOSI
MISO
_SS
SCK
shift register
MOSI
MISO
MISO
_SS
SCK
SPI Master
SPI Slave 0
_SS[n-1]
SPI Slave n-1