Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
843
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
event. The events must be correctly routed in the Event System. Refer to
for
details.
The peripheral can take the following actions on an input event:
z
ADC start conversion (START)
z
ADC conversion flush (FLUSH)
Input events must be enabled for the corresponding action to be taken on any input event. Writing a one to an Event
Input bit in the Event Control register (EVCTRL.xxEI) enables the corresponding action on the input event. Writing a zero
to this bit disables the corresponding action on the input event. Note that if several events are connected to the
peripheral, the enabled action will be taken on any of the incoming events. The events must be correctly routed in the
Event System. Refer to
Input bit in the Event Control register (EVCTRL.xxEI) enables the corresponding action on the input event. Writing a zero
to this bit disables the corresponding action on the input event. Note that if several events are connected to the
peripheral, the enabled action will be taken on any of the incoming events. The events must be correctly routed in the
Event System. Refer to
32.6.12 Sleep Mode Operation
The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC during standby
sleep mode. When the bit is zero, the ADC is disabled during sleep, but maintains its current configuration. When
the bit is one, the ADC continues to operate during sleep. Note that when RUNSTDBY is zero, the analog
blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system
returns from sleep.
When RUNSTDBY is one, any enabled ADC interrupt source can wake up the CPU. While the CPU is sleeping, ADC
conversion can only be triggered by events.
sleep mode. When the bit is zero, the ADC is disabled during sleep, but maintains its current configuration. When
the bit is one, the ADC continues to operate during sleep. Note that when RUNSTDBY is zero, the analog
blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system
returns from sleep.
When RUNSTDBY is one, any enabled ADC interrupt source can wake up the CPU. While the CPU is sleeping, ADC
conversion can only be triggered by events.
32.6.13 Synchronization
Due to the asynchronicity between CLK_ADC_APB and GCLK_ADC, some registers must be synchronized when
accessed. A register can require:
accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z
Software Reset bit in the Control A register (CTRLA.SWRST)
z
Enable bit in the Control A register (CTRLA.ENABLE)
The following registers need synchronization when written:
z
Control B (CTRLB)
z
Software Trigger (SWTRIG)
z
Window Monitor Control (WINCTRL)
z
Input Control (INPUTCTRL)
z
Window Upper/Lower Threshold (WINUT/WINLT)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers need synchronization when read:
z
Software Trigger (SWTRIG)
z
Input Control (INPUTCTRL)
z
Result (RESULT)