Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
85
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Figure 14-2. Generic Clock Controller Block Diagram
Note:
1. If the GENCTRL.SRC=GCLKIN the GCLK_IO is set as an input.
14.4 Signal Description
for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
14.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
14.5.1 I/O Lines
Using the Generic Clock Controller’s I/O lines requires the I/O pins to be configured. Refer to
details.
14.5.2 Power Management
The Generic Clock Controller can operate in all sleep modes, if required. Refer to
sleep modes.
14.5.3 Clocks
The Generic Clock Controller bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the
default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section in
default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section in
Generic Clock Generator 0
GCLK_IO[0]
(I/O input)
Clock
Divider &
Masker
Divider &
Masker
Clock Sources
GCLKGEN[0]
GCLK_IO[1]
(I/O input)
GCLKGEN[1]
GCLK_IO[n]
(I/O input)
GCLKGEN[n]
Clock
Gate
Gate
Generic Clock Multiplexer 0
GCLK_PERIPHERAL[0]
Clock
Gate
Gate
Generic Clock Multiplexer 1
Clock
Gate
Gate
Generic Clock Multiplexer m
GCLKGEN[n:0]
GCLK_MAIN
GCLK_IO[1]
(I/O output)
GCLK_IO[0]
(I/O output)
GCLK_IO[n]
(I/O output)
Generic Clock Generator 1
Clock
Divider &
Masker
Divider &
Masker
Generic Clock Generator n
Clock
Divider &
Masker
Divider &
Masker
GCLK_PERIPHERAL[1]
GCLK_PERIPHERAL[m]
Table 14-1. Signal Description
Signal Name
Type
Description
GCLK_IO[7:0]
Digital I/O
Source clock when input
Generic clock when output
Generic clock when output