Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
87
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Refer to
3.
The generic clock must be configured by performing a single 16-bit write to the Generic Clock Control register
(CLKCTRL):
(CLKCTRL):
z
The generic clock that will be configured must be written to the ID bit group (CLKCTRL.ID)
z
The generic clock generator used as the source of the generic clock must be written to the GEN bit group
(CLKCTRL.GEN)
(CLKCTRL.GEN)
Refer to
register for details.
14.6.2.2 Enabling, Disabling and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
GCLK will be reset to their initial state except for generic clocks and associated generators that have their Write Lock bit
written to one. Refer to
GCLK will be reset to their initial state except for generic clocks and associated generators that have their Write Lock bit
written to one. Refer to
14.6.2.3 Generic Clock Generator
Each generic clock generator (GCLKGEN) can be set to run from one of eight different clock sources except
GCLKGEN[1] which can be set to run from one of seven sources. GCLKGEN[1] can act as source to the other generic
clock generators but can not act as source to itself.
GCLKGEN[1] which can be set to run from one of seven sources. GCLKGEN[1] can act as source to the other generic
clock generators but can not act as source to itself.
Each generic clock generator GCLKGEN[x] can be connected to one specific GCLK_IO[x] pin. The GCLK_IO[x] can be
set to act as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by GCLKGEN[x].
set to act as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by GCLKGEN[x].
The selected source (GCLKGENSRC see
) can optionally be divided. Each generic clock generator can be
independently enabled and disabled.
Each GCLKGEN clock can then be used as a clock source for the generic clock multiplexers. Each generic clock is
allocated to one or several peripherals.
allocated to one or several peripherals.
GCLKGEN[0], is used as GCLK_MAIN for the synchronous clock controller inside the Power Manager.
Figure 14-3. Generic Clock Generator
14.6.2.4 Enabling a Generic Clock Generator
A generic clock generator is enabled by writing a one to the Generic Clock Generator Enable bit in the Generic Clock
Generator Control register (GENCTRL.GENEN).
Generator Control register (GENCTRL.GENEN).
14.6.2.5 Disabling a Generic Clock Generator
A generic clock generator is disabled by writing a zero to GENCTRL.GENEN. When GENCTRL.GENEN is read as zero,
the GCLKGEN clock is disabled and clock gated.
the GCLKGEN clock is disabled and clock gated.
GCLK_IO[x]
DIVIDER
Clock
Gate
Gate
GCLKGEN[x]
Clock Sources
0
1
GENCTRL.DIVSEL
GENCTRL.GENEN
GENDIV.DIV
GENCTRL.SRC
GCLKGENSRC