Linear Technology DC1369A-G - LTC2261-12: 12-bit, 125Msps ADC, LVDS Outputs, 5-170MHz, req DC890, LVDS_XFMR and DC1075 D DC1369A-G Fiche De Données

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dc1369af

DEMO MANUAL DC1369A

Serial Programming
PScope has the ability to program the DC1369A board 

serially through the DC890. There are several options 

available in the LTC2262 family that are only available 

through serially programming.  PScope allows all of these 

features to be tested.  
These options are available by first clicking on the Set 

Demo Bd Options icon on the PScope toolbar (Figure 3).
This will bring up the menu shown in Figure 4.

This menu allows any of the options available for the 

LTC2262 family to be programmed serially. The LTC2262 

family has the following options:
Power Control: Selects between normal operation, nap, 

and sleep modes
•  Normal (Default): Entire ADC is powered, and active
•  Nap:  ADC  core  powers  down  while  references  stay

active

•  Shutdown: The entire ADC is powered down
Clock Inversion: Selects the polarity of the CLKOUT signal
•  Normal (Default): Normal CLKOUT polarity
•  Inverted: CLKOUT polarity is inverted

Clock Delay: Selects the phase delay of the CLKOUT  

signal
•  None (Default): No CLKOUT delay
•  45 deg: CLKOUT delayed by 45 degrees
•  90 deg: CLKOUT delayed by 90 degrees
•  135 deg: CLKOUT delayed by 135 degrees

Clock Duty Cycle: Enable or Disables Duty Cycle Stabilizer
•  Stabilizer Off (Default): Duty cycle stabilizer disabled
•  Stabilizer On: Duty cycle stabilizer enabled

Output Current: Selects the LVDS output drive current
•  1.75mA (Default): LVDS output driver current
•  2.1mA: LVDS output driver current
•  2.5mA: LVDS output driver current
•  3.0mA: LVDS output driver current
•  3.5mA: LVDS output driver current
•  4.0mA: LVDS output driver current
•  4.5mA: LVDS output driver current