Linear Technology DC1369A-G - LTC2261-12: 12-bit, 125Msps ADC, LVDS Outputs, 5-170MHz, req DC890, LVDS_XFMR and DC1075 D DC1369A-G Fiche De Données

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dc1369af

DEMO MANUAL DC1369A

Internal Termination: Enables LVDS Internal Termination
•  Off (Default): Disables internal termination
•  On: Enables internal termination

Outputs: Enables Digital Outputs
•  Enabled (Default): Enables digital outputs
•  Disabled: Disables digital outputs

Output Mode: Selects Digital Output Mode
•  Full Rate: Full rate CMOS output mode (This mode is

not supported by the DC1369A, please use the DC1370)

•  Double LVDS (Default): Double data rate LVDS output

mode

•  Double CMOS: Double data rate CMOS output mode

(This mode is not supported by the DC1369A, please 

use the DC1370)

Test Pattern: Selects Digital Output Test Patterns
•  Off (Default): ADC data presented at output
•  All Out = 1: All digital outputs are 1
•  All Out = 0: All digital outputs are 0
•  Checkerboard: OF, and D13-D0 Alternate between 101

0101 1010 0101 and 010 1010 0101 1010 on alternat-

ing samples.

•  Alternating: Digital outputs alternate between all 1’s and

all 0’s on alternating samples.

Alternate Bit: Alternate Bit Polarity (ABP) Mode 
•  Off (Default): Disables alternate bit polarity
•  On: Enables alternate bit polarity (Before enabling ABP,

be sure the part is in offset binary mode)

Randomizer: Enables Data Output Randomizer
•  Off (Default): Disables data output randomizer
•  On: Enables data output randomizer

Two’s Complement: Enables Two’s Complement Mode
•  Off (Default): Selects offset binary mode
•  On: Selects two’s complement mode

Once the desired settings are selected hit OK and PScope 

will automatically update the register of the device on the 

DC1369A demo board.