On Semiconductor NCP3065 Evaluation Boards NCP3065SOBCKGEVB and NCP3065SOBSTGEVB NCP3065SOBCKGEVB NCP3065SOBCKGEVB Fiche De Données

 (measured vs. pin 4, unless otherwise noted)

V

CC

 (Pin 6)

V

CC

0 to +40

V

Comparator Inverting Input (Pin 5)

V

CII

−0.2 to +V

CC

V

Darlington Switch Collector (Pin 1)

V

SWC

0 to +40

V

Darlington Switch Emitter (Pin 2) (Transistor OFF)

V

SWE

−0.6 to +V

CC

V

Darlington Switch Collector to Emitter (Pins 1−2)

V

SWCE

0 to +40

V

Darlington Switch Current

I

SW

1.5

A

I

pk

 Sense (Pin 7)

V

IPK

−0.2 to

 

V

CC

 + 0.2

V

Timing Capacitor (Pin 3)

V

TCAP

−0.2 to

 

+1.4

V

PDIP−8

Thermal Resistance Junction−to−Air

R

qJA

100

°C/W

SOIC−8

Thermal Resistance Junction−to−Air

R

qJA

180

°C/W

DFN−8

Thermal Resistance Junction−to−Air

Thermal Resistance Junction−to−Case

R

qJA

R

qJC

78

14

°C/W

Storage Temperature Range

T

STG

−65 to +150

°C

Maximum Junction Temperature

T

J(MAX)

+150

°C

Operating Junction Temperature Range (Note 3)

NCP3065, NCV3065

T

J

−40 to +125

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Pin 1−8: Human Body Model 2000 V per AEC Q100−002; 003 or JESD22/A114; A115

Machine Model Method 200 V

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is T

J

 = T

A

 + R

q • 

P

D

4. The pins which are not defined may not be loaded by external signals