STMicroelectronics Evaluation board for A5970AD EVALA5970AD EVALA5970AD Fiche De Données
Codes de produits
EVALA5970AD
Closing the loop
A5970AD
20/42
DocID14661 Rev 5
Example 1
Considering R
C
= 1.8 k
, C
C
= 68nF and C
P
= 330 pF, the poles and zeroes of A
0
are:
F
P1
= 2.9 Hz
F
P2
= 265 kHz
F
Z1
= 1.3 kHz
If L = 15 µH, C
OUT
= 330 µF and ESR = 55 m
, the poles and zeroes of A
LC
become:
F
PLC
= 2.5 kHz
F
ZESR
= 8.7 kHz
Finally R
1
= 5.6 k
and R
2
= 3.3 k
.
The gain and phase bode diagrams are plotted respectively in
and
.
Figure 11. Module plot
Figure 12. Phase plot
The cut-off frequency and the phase margin are:
Equation 16
F
C
24KHz
=
Phase margin = 64°