Texas Instruments SM320F2812-HT Manuel D’Utilisation
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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Contents
1
Features
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1.1
SUPPORTS EXTREME TEMPERATURE APPLICATIONS
.........................................................
2
Introduction
......................................................................................................................
2.1
Description
.................................................................................................................
2.2
Device Summary
..........................................................................................................
2.3
Die Layout
..................................................................................................................
2.4
Pin Assignments
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2.5
Signal Descriptions
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3
Functional Overview
..........................................................................................................
3.1
Memory Map
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3.2
Brief Descriptions
..........................................................................................................
3.2.1
C28x CPU
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3.2.2
Memory Bus (Harvard Bus Architecture)
....................................................................
3.2.3
Peripheral Bus
..................................................................................................
3.2.4
Real-Time JTAG and Analysis
................................................................................
3.2.5
External Interface (XINTF)
....................................................................................
3.2.6
Flash
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3.2.7
L0, L1, H0 SARAMs
............................................................................................
3.2.8
Boot ROM
.......................................................................................................
3.2.9
Security
..........................................................................................................
3.2.10
Peripheral Interrupt Expansion (PIE) Block
.................................................................
3.2.11
External Interrupts (XINT1, XINT2, XINT13, XNMI)
........................................................
3.2.12
Oscillator and PLL
..............................................................................................
3.2.13
Watchdog
........................................................................................................
3.2.14
Peripheral Clocking
.............................................................................................
3.2.15
Low-Power Modes
..............................................................................................
3.2.16
Peripheral Frames 0, 1, 2 (PFn)
..............................................................................
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer
.........................................................
3.2.18
32-Bit CPU Timers (0, 1, 2)
...................................................................................
3.2.19
Control Peripherals
.............................................................................................
3.2.20
Serial Port Peripherals
.........................................................................................
3.3
Register Map
...............................................................................................................
3.4
Device Emulation Registers
..............................................................................................
3.5
External Interface, XINTF
................................................................................................
3.5.1
Timing Registers
................................................................................................
3.5.2
XREVISION Register
...........................................................................................
3.6
Interrupts
....................................................................................................................
3.6.1
External Interrupts
..............................................................................................
3.7
System Control
............................................................................................................
3.8
OSC and PLL Block
.......................................................................................................
3.8.1
Loss of Input Clock
.............................................................................................
3.9
PLL-Based Clock Module
................................................................................................
3.10
External Reference Oscillator Clock Option
...........................................................................
3.11
Watchdog Block
...........................................................................................................
3.12
Low-Power Modes Block
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2
Contents
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