Nxp Semiconductors TDA8752B Manuel D’Utilisation

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The ADCs are 8-bit with a maximum clock frequency of 110 Msps. The ADCs input
range is 1 V (p-p) full-scale. One out of range bit exists per channel (ROR, GOR and
BOR). It will be at logic 1 when the signal is out of range of the full-scale of the ADCs.

Pipeline delay in the ADCs is 1 clock cycle from sampling to data output.

The ADCs reference ladders regulators are integrated.

ADC outputs are straight binary. An output enable pin (OE; active LOW) enables the
output status between active and high-impedance (OE = HIGH) to be switched; it is
recommended to load the outputs with a 10 pF capacitive load. The timing must be
checked very carefully if the capacitive load is more than 10 pF.

The ADCs are clocked either by an internal PLL locked to the CKREF clock (all of the
PLL is on-chip except the loop filter capacitance) or by an external clock applied to
pin CKEXT. Selection is performed via the serial interface bus.

The reference clock (CKREF) range is between 15 and 280 kHz. Consequently, the
VCO minimum frequency is 12 MHz and the maximum frequency is 110 MHz. The
gain of the VCO part can be controlled via the serial interface, depending on the
frequency range to which the PLL is locked.

To increase the bandwidth of the PLL, the charge pump current, controlled by the
serial interface, must also be increased. The relationship between the frequency and
the current is given by the following equation:

(1)

FCE473

128

160

227

255

G(max)

GNCOARSE

NCOARSE

G(min)

ADC

output code

coarse

register

value

(67 codes)

NFINE = 31

NFINE = 0

Vref

π

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