Manuels d'utilisation pour Cisco Intel Xeon E7-4850

Table des matières

• 1 Introduction

  7
  • 1.1 Intel® Xeon® Processor E7-8800/4800/2800 Product Families Features

    7
  • 1.2 Terminology and Conventions

    9
    • 1.2.1 Abbreviations

      9
  • 1.3 Notational Conventions

    11
    • 1.3.1 Hexadecimal and Binary Numbers

      11
• 2 Intel Xeon Processor E7-8800/ 4800/2800 Product Families Architecture

  13
  • 2.1 Introduction

    13
    • 2.1.1 Intel® Xeon® Processor 7500 Series-Based Platform Overview

      14
  • 2.2 Intel Xeon Processor E7-8800/4800/2800 Product Families Components (Boxes)

    15
• 3 Address Map

  17
  • 3.1 NodeID Generation

    17
    • 3.1.1 DRAM Decoder

      17
    • 3.1.2 I/O Decoder Map

      18
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    19
    • 3.2.1 Key Concepts

      19
• 4 LLC Coherence Engine (Cbox) and Caching Agent (Sbox)

  21
  • 4.1 Last Level Cache

    21
    • 4.1.1 LLC Major Features

      22
  • 4.2 RTID Generation

    22
• 5 Home Agent and Global Coherence Engine (Bbox)

  25
  • 5.1 Tracker Allocation Modes

    25
    • 5.1.1 The Tracker Modes

      26
  • 5.2 Directory Assisted Snoopy (DAS)

    27
  • 5.3 IO Directory Cache (IODC)

    27
• 6 System Configuration Controller (Ubox)

  29
  • 6.1 Introduction

    29
• 7 Memory Controller (Mbox)

  31
  • 7.1 New Features on Intel Xeon Processor E7-8800/ 4800/2800 Product Families

    31
  • 7.2 Memory Controller (Mbox) Support

    31
  • 7.3 Double Device Data Correction (DDDC)

    32
    • 7.3.1 DDDC flow overview

      32
    • 7.3.2 DDDC Constraints

      32
  • 7.4 Leaky Bucket Error Counters

    32
    • 7.4.1 Per Rank Memory Error Counter

      32
    • 7.4.2 Error Flow Counters

      32
  • 7.5 Partial Memory Mirroring

    33
    • 7.5.1 Usage Model

      33
    • 7.5.2 Overview

      33
  • 7.6 Mirroring Mode Restrictions

    35
  • 7.7 Intel® Dynamic Power Technology (Intel® DPT)

    35
    • 7.7.1 Memory Power States

      36
• 8 Physical Layer (Pbox)

  37
  • 8.1 Intel Xeon Processor E7-8800/4800/2800 Product Families Pbox Functional Overview

    37
  • 8.2 Intel® SMI Port specific deltas

    37
  • 8.3 Intel® QPI Port specific deltas

    37
• 9 Power Management Architecture (Wbox)

  39
  • 9.1 Thermal Management

    39
    • 9.1.1 Thermal Monitoring - 2 (TM2)

      39
    • 9.1.2 Thermal Monitoring - 1 (TM1) and T-state

      39
    • 9.1.3 THERMTRIP#

      40
    • 9.1.4 PROCHOT#

      40
    • 9.1.5 FORCEPR#

      40
    • 9.1.6 PECI

      40
  • 9.2 Idle State Power Management

    40
    • 9.2.1 Overview

      40
    • 9.2.2 C-State Support

      41
  • 9.3 Core C6 Support

    45
    • 9.3.1 Core C6

      45
    • 9.3.2 Core C6 Entry/Exit Flow

      45
  • 9.4 Package C6 Support

    45
    • 9.4.1 Introduction

      46
  • 9.5 Package C3/Package C6 with Memory Self Refresh

    46
    • 9.5.1 Package C3/C6 Memory Self-Refresh Limitations

      46
    • 9.5.2 PMReq Retry/CmpD Response Behavior

      47
  • 9.6 S-State Support

    48
    • 9.6.1 Overview

      48
  • 9.7 APIC Timer

    48
  • 9.8 PECI Sideband P-state Control

    48
    • 9.8.1 Overview

      48
    • 9.8.2 MAILBOX_WRITE_P_STATE_LIMIT (request type = 0x23)

      48
    • 9.8.3 MAILBOX_READ_P_STATE_LIMIT (request type = 0x24)

      49