Cisco Intel Xeon E7-4850 사용자 매뉴얼

차례

• 1 Introduction

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  • 1.1 Intel® Xeon® Processor E7-8800/4800/2800 Product Families Features

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  • 1.2 Terminology and Conventions

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    • 1.2.1 Abbreviations

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  • 1.3 Notational Conventions

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    • 1.3.1 Hexadecimal and Binary Numbers

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• 2 Intel Xeon Processor E7-8800/ 4800/2800 Product Families Architecture

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  • 2.1 Introduction

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    • 2.1.1 Intel® Xeon® Processor 7500 Series-Based Platform Overview

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  • 2.2 Intel Xeon Processor E7-8800/4800/2800 Product Families Components (Boxes)

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• 3 Address Map

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  • 3.1 NodeID Generation

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    • 3.1.1 DRAM Decoder

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    • 3.1.2 I/O Decoder Map

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  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

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    • 3.2.1 Key Concepts

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• 4 LLC Coherence Engine (Cbox) and Caching Agent (Sbox)

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  • 4.1 Last Level Cache

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    • 4.1.1 LLC Major Features

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  • 4.2 RTID Generation

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• 5 Home Agent and Global Coherence Engine (Bbox)

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  • 5.1 Tracker Allocation Modes

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    • 5.1.1 The Tracker Modes

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  • 5.2 Directory Assisted Snoopy (DAS)

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  • 5.3 IO Directory Cache (IODC)

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• 6 System Configuration Controller (Ubox)

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  • 6.1 Introduction

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• 7 Memory Controller (Mbox)

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  • 7.1 New Features on Intel Xeon Processor E7-8800/ 4800/2800 Product Families

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  • 7.2 Memory Controller (Mbox) Support

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  • 7.3 Double Device Data Correction (DDDC)

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    • 7.3.1 DDDC flow overview

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    • 7.3.2 DDDC Constraints

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  • 7.4 Leaky Bucket Error Counters

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    • 7.4.1 Per Rank Memory Error Counter

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    • 7.4.2 Error Flow Counters

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  • 7.5 Partial Memory Mirroring

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    • 7.5.1 Usage Model

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    • 7.5.2 Overview

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  • 7.6 Mirroring Mode Restrictions

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  • 7.7 Intel® Dynamic Power Technology (Intel® DPT)

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    • 7.7.1 Memory Power States

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• 8 Physical Layer (Pbox)

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  • 8.1 Intel Xeon Processor E7-8800/4800/2800 Product Families Pbox Functional Overview

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  • 8.2 Intel® SMI Port specific deltas

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  • 8.3 Intel® QPI Port specific deltas

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• 9 Power Management Architecture (Wbox)

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  • 9.1 Thermal Management

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    • 9.1.1 Thermal Monitoring - 2 (TM2)

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    • 9.1.2 Thermal Monitoring - 1 (TM1) and T-state

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    • 9.1.3 THERMTRIP#

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    • 9.1.4 PROCHOT#

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    • 9.1.5 FORCEPR#

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    • 9.1.6 PECI

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  • 9.2 Idle State Power Management

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    • 9.2.1 Overview

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    • 9.2.2 C-State Support

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  • 9.3 Core C6 Support

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    • 9.3.1 Core C6

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    • 9.3.2 Core C6 Entry/Exit Flow

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  • 9.4 Package C6 Support

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    • 9.4.1 Introduction

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  • 9.5 Package C3/Package C6 with Memory Self Refresh

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    • 9.5.1 Package C3/C6 Memory Self-Refresh Limitations

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    • 9.5.2 PMReq Retry/CmpD Response Behavior

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  • 9.6 S-State Support

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    • 9.6.1 Overview

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  • 9.7 APIC Timer

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  • 9.8 PECI Sideband P-state Control

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    • 9.8.1 Overview

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    • 9.8.2 MAILBOX_WRITE_P_STATE_LIMIT (request type = 0x23)

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    • 9.8.3 MAILBOX_READ_P_STATE_LIMIT (request type = 0x24)

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