Manuel D’UtilisationTable des matièresFront cover1Contents7Notices11Trademarks12Preface13The team that wrote this redbook13Become a published author14Comments welcome14Chapter 1. IBM zSeries 990 overview151.1 Introduction171.2 z990 models181.3 System functions and features191.3.1 Processor191.3.2 Memory201.3.3 Self-Timed Interconnect (STI)201.3.4 Channel Subsystem (CSS)201.3.5 Physical Channel IDs (PCHIDs) and CHPID Mapping Tool211.3.6 Spanned channels211.3.7 I/O connectivity221.3.8 Cryptographic261.3.9 Parallel Sysplex support271.3.10 Intelligent Resource Director (IRD)291.3.11 Hardware consoles291.3.12 Concurrent upgrades301.3.13 Performance311.3.14 Reliability, Availability, Serviceability (RAS)321.3.15 Software321.3.16 Software support341.3.17 Summary36Chapter 2. System structure and design372.1 System structure382.1.1 Book concept382.1.2 Models402.1.3 Memory412.1.4 Ring Topology432.1.5 Connectivity452.1.6 Frames and cages472.1.7 The MCM492.1.8 The PU, SC, and SD chips502.1.9 Summary512.2 System design512.2.1 Design highlights522.2.2 Book design532.2.3 Processor Unit design552.2.4 Processor unit functions602.2.5 Memory design672.2.6 Modes of operation702.2.7 Model configurations752.2.8 Storage operations812.2.9 Reserved storage842.2.10 LPAR storage granularity842.2.11 LPAR Dynamic Storage Reconfiguration (DSR)852.2.12 I/O subsystem852.2.13 Channel Subsystem86Chapter 3. I/O system structure873.1 Overview883.2 I/O cages893.2.1 Self-Timed Interconnect (STI)913.2.2 STIs and I/O cage connections913.2.3 Balancing I/O connections933.3 I/O and cryptographic feature cards983.3.1 I/O feature cards983.3.2 Cryptographic feature cards993.3.3 Physical Channel IDs (PCHIDs)1003.4 Connectivity1033.4.1 I/O and cryptographic features support and configuration rules1033.4.2 ESCON channel1073.4.3 FICON channel1103.4.4 OSA-Express adapter1123.4.5 Coupling Facility links1173.4.6 External Time Reference (ETR) feature1203.4.7 Cryptographic features121Chapter 4. Channel Subsystem1234.1 Multiple Logical Channel Subsystem (LCSS)1244.1.1 Logical Channel Subsystem structure1244.1.2 Physical Channel ID (PCHID)1274.1.3 Channel spanning1284.2 LCSS configuration management1294.2.1 z990 configuration management1304.3 LCSS-related numbers131Chapter 5. Cryptography1335.1 Cryptographic function support1345.1.1 Cryptographic Synchronous functions1345.1.2 Cryptographic Asynchronous functions1345.2 z990 Cryptographic processors1365.2.1 CP Assist for Cryptographic Function (CPACF)1365.2.2 PCIX Cryptographic Coprocessor (PCIXCC)1375.2.3 PCI Cryptographic Accelerator (PCICA) feature1385.3 Cryptographic hardware features1395.3.1 PCIX Cryptographic Coprocessor feature1395.3.2 The PCICA feature1405.3.3 Configuration rules1405.3.4 z990 cryptographic feature codes1415.3.5 TKE workstation feature1425.4 Cryptographic features comparison1425.5 Software requirements143Chapter 6. Software support1476.1 Operating system support1486.2 z/OS software support1486.2.1 Compatibility support for z/OS1486.2.2 Exploitation support for z/OS1516.2.3 HCD support1546.2.4 Automation changes1546.2.5 SMF support1546.2.6 RMF support1556.2.7 ICKDSF requirements1556.2.8 ICSF support1566.2.9 Additional exploitation support considerations1566.3 z/VM software support1596.4 z/VSE and VSE/ESA software support1606.5 TPF software support1606.6 Linux software support1606.7 Summary of software requirements1616.7.1 Summary of z/OS and OS/390 software requirements1616.7.2 Summary of z/VM, z/VSE, VSE/ESA, TPF, and Linux Software Requirements1626.8 Workload License Charges1646.9 Concurrent upgrades considerations165Chapter 7. Sysplex functions1677.1 Parallel Sysplex1687.1.1 Parallel Sysplex described1687.1.2 Parallel Sysplex summary1717.2 Sysplex and Coupling Facility considerations1717.2.1 Sysplex configurations and Sysplex Timer considerations1717.2.2 Coupling Facility and CFCC considerations1747.2.3 CFCC enhanced patch apply1747.2.4 Coupling Facility link connectivity1767.2.5 Coupling Facility Resource Manager (CFRM) policy considerations1787.2.6 ICF processor assignments1787.2.7 Dynamic CF dispatching and dynamic ICF expansion1807.3 System-managed CF structure duplexing1817.3.1 Benefits1817.3.2 CF Structure Duplexing1827.3.3 Configuration planning1827.4 Geographically Dispersed Parallel Sysplex1847.4.1 GDPS/PPRC1847.4.2 GDPS/XRC1887.4.3 GDPS and Capacity Backup (CBU)1897.5 Intelligent Resource Director1907.5.1 LPAR CPU management1917.5.2 Dynamic Channel Path Management1927.5.3 Channel Subsystem Priority Queueing1947.5.4 WLM and Channel Subsystem priority1957.5.5 Special considerations and restrictions1967.5.6 References197Chapter 8. Capacity upgrades1998.1 Concurrent upgrades2008.2 Capacity Upgrade on Demand (CUoD)2028.3 Customer Initiated Upgrade (CIU)2088.4 On/Off Capacity on Demand (On/Off CoD)2148.5 Capacity BackUp (CBU)2188.6 Nondisruptive upgrades2228.6.1 Upgrade scenarios2238.6.2 Planning for nondisruptive upgrades2298.7 Capacity planning considerations2318.7.1 Balanced system design2328.7.2 Superscalar processors2348.7.3 Integrated hardware and system assists2358.8 Capacity measurements2368.8.1 Large Systems Performance Reference (LSPR)237Chapter 9. Environmentals2439.1 Introduction2449.1.1 Power and cooling requirements2449.1.2 Power consumption2449.1.3 Internal Battery Feature2449.1.4 Emergency power-off2459.1.5 Cooling requirements2459.2 Weights2459.3 Dimensions246Appendix A. Hardware Management Console (HMC)247Introduction247z990 Hardware Management Console249Token ring only wiring scenario250Ethernet only - one-path wiring scenario251Ethernet only - two-path wiring scenario253Token ring and Ethernet wiring scenario255Remote operations256Support Element257z990 HMC enhancements257Appendix B. Fiber optic cabling services261Related publications265IBM Redbooks265Other publications265Online resources266How to get IBM Redbooks266Glossary267Index277Back cover282Taille: 4 MoPages: 282Language: EnglishOuvrir le manuel