Manuels d'utilisation pour Intel 82801EB

Table des matières

• Title Page

  1
• Contents

  3
• Revision History

  6
• Introduction

  7
  • About This Document

    7
  • Reference Documents and Information Sources

    9
• Overview

  11
  • Intel® ICH5 AC ’97 Controller Compatibility

    11
    • Third AC ’97 Component Specification Revision 2.1, Revision 2.2 and Revision 2.3 Compliant Codecs

      14
    • Dedicated S/P DIF DMA Output Channel

      15
    • 20 Bits Surround PCM Output

      15
    • Memory Map Status and Control Registers

      15
    • Second Independent Input DMA Engines

      16
    • PCI Local Bus Specification, Revision 2.3 Power Management

      16
  • General Requirements

    16
• Intel® ICH5 AC ’97 Controller Theory of Operation

  17
  • Intel® ICH5 AC ’97 Initialization

    17
    • System Reset

      17
    • Codec Topology

      17
    • BIOS PCI Configuration

      18
    • Hardware Interrupt Routing

      19
    • PCI Lock

      19
  • DMA Engines

    20
    • Buffer Descriptor List

      20
    • DMA Initialization

      21
    • DMA Steady State Operation

      23
    • Stopping Transfers

      24
    • FIFO Error Conditions

      24
      • FIFO Underrun

        24
      • FIFO Overrun

        24
  • Channel Arbitration

    25
  • Data Buffers

    25
    • Memory Organization of Data

      25
    • PCM Buffer Restrictions

      25
    • FIFO Organization

      26
  • Multiple Codec/Driver Support

    27
    • Codec Register Shadowing

      28
    • Codec Access Synchronization

      29
    • Data Request Synchronization in Audio Split Configurations

      29
  • Power Management

    30
    • Codec Topologies

      30
      • Tertiary Codec Topologies

        31
    • Power Management Transition Maps

      31
      • Configuration Number 1: Single Audio Codec (Primary):

        32
      • Configuration Number 2: Single Modem Codec (Primary):

        32
      • Configuration Numbers 3 to 6: Dual Function Single or Dual Codec Configurations:

        33
    • Power Management Topology Considerations

      34
      • Determining the Presence of Secondary and Tertiary Codecs

        34
      • Determining the Presence of a Modem Function

        35
    • Resume Context Recovery

      35
    • Aggressive Power Management

      35
      • Primary Audio Requested to D3

        36
      • Secondary Modem Requested to D3

        36
      • Secondary Modem Requested to D0

        36
      • Audio Primary Requested to D0

        37
      • Using a Cold or Warm Reset

        37
• Surround Audio Support

  39
  • Determine Codec’s Audio Channels

    39
  • Enabling Intel® ICH5 AC ’97 Controller Audio Channels

    40
• 20-Bits PCM Support

  43
• Independent S-P/DIF Output Capability

  45
• Support for Double Rate Audio

  47
• Independent Input Channels Capability

  49
  • Link Topology Determination

    49
• Intel® ICH5 AC ’97 Modem Driver

  51
  • Robust Host-Based Generation of a Synchronous Data Stream

    51
    • Spurious Data Algorithm

      52
    • Intel® ICH5 AC ’97 Spurious Data Implementation

      52