Manuel D’UtilisationTable des matièresTitle Page1Contents3Revision History8Introduction11Terminology and Notations11Reference Documents13Intel® 845 Chipset System Architecture14Intel® 82845 MCH Overview14System Bus Interface15System Bus Error Checking15System Memory Interface16AGP Interface16Hub Interface17Intel® MCH Clocking17System Interrupts18Powerdown Flow18Signal Description19System Bus Signals21SDR SDRAM Interface Signals23AGP Addressing Signals24AGP Flow Control Signals25Register Description31Register Terminology31Standard PCI Bus Configuration Mechanism33Routing Configuration Accesses33I/O Mapped Registers34CONF_ADDR—Configuration Address Register34CONF_DATA—Configuration Data Register36Memory-Mapped Register Space36DRAMWIDTH—DRAM Width Register37DQCMDSTR—Strength Control Register (SDQ and CMD Signal Groups)38CKESTR—Strength Control Register (SCKE Signal Group)39CSBSTR—Strength Control Register (SCS# Signal Group)40CKSTR—Strength Control Register (Clock Signal Group)41RCVENSTR—Strength Control Register (RCVENOUT Signal Group)42Host-Hub Interface Bridge Device Registers (Device 0)43VID—Vendor Identification Register (Device 0)45DID—Device Identification Register (Device 0)45PCICMD—PCI Command Register (Device 0)46PCISTS—PCI Status Register (Device 0)47RID—Revision Identification Register (Device 0)48SUBC—Sub-Class Code Register (Device 0)48BCC—Base Class Code Register (Device 0)48MLT—Master Latency Timer Register (Device 0)49HDR—Header Type Register (Device 0)49APBASE—Aperture Base Configuration Register (Device 0)50SVID—Subsystem Vendor Identification (Device 0)51SID—Subsystem Identification (Device 0)51CAPPTR—Capabilities Pointer (Device 0)51AGPM—AGP Miscellaneous Configuration Register (Device 0)52DRB[0:7]—DRAM Row Boundary Registers (Device 0)52DRA—DRAM Row Attribute Registers (Device 0)53DRT—DRAM Timing Register (Device 0)55DRC—DRAM Controller Mode Register (Device 0)56DERRSYN—DRAM Error Syndrome Register (Device 0)58EAP—Error Address Pointer Register (Device 0)58PAM[0:6]—Programmable Attribute Map Registers (Device 0)59FDHC—Fixed DRAM Hole Control Register (Device 0)62SMRAM—System Management RAM Control Register (Device 0)63ESMRAMC—Extended System Mgmt RAM Control Register (Device 0)64ACAPID—AGP Capability Identifier Register (Device 0)65AGPSTAT—AGP Status Register (Device 0)66AGPCMD—AGP Command Register (Device 0)67AGPCTRL—AGP Control Register (Device 0)68APSIZE—Aperture Size (Device 0)69ATTBASE—Aperture Translation Table Base Register (Device 0)70AMTT—AGP Interface Multi-Transaction Timer Register (Device 0)71LPTT—AGP Low Priority Transaction Timer Register (Device 0)72TOM—Top of Low Memory Register (Device 0)73MCHCFG—MCH Configuration Register (Device 0)74ERRSTS—Error Status Register (Device 0)75ERRCMD—Error Command Register (Device 0)76SMICMD—SMI Command Register (Device 0)78SCICMD—SCI Command Register (Device 0)78SKPD—Scratchpad Data Register (Device 0)79CAPID—Product Specific Capability Identifier Register (Device 0)79Bridge Registers (Device 1)80VID1—Vendor Identification Register (Device 1)81DID1—Device Identification Register (Device 1)81PCICMD1—PCI-PCI Command Register (Device 1)82PCISTS1—PCI-PCI Status Register (Device 1)83RID1—Revision Identification Register (Device 1)84SUBC1—Sub-Class Code Register (Device 1)84BCC1—Base Class Code Register (Device 1)84MLT1—Master Latency Timer Register (Device 1)85HDR1—Header Type Register (Device 1)85PBUSN1—Primary Bus Number Register (Device 1)85SBUSN1—Secondary Bus Number Register (Device 1)86SUBUSN1—Subordinate Bus Number Register (Device 1)86SMLT1—Secondary Master Latency Timer Register (Device 1)87IOBASE1—I/O Base Address Register (Device 1)88IOLIMIT1—I/O Limit Address Register (Device 1)88SSTS1—Secondary PCI-PCI Status Register (Device 1)89MBASE1—Memory Base Address Register (Device 1)90MLIMIT1—Memory Limit Address Register (Device 1)90PMBASE1—Prefetchable Memory Base Address Register (Device 1)91PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)91BCTRL1—PCI-PCI Bridge Control Register (Device 1)92ERRCMD1—Error Command Register (Device 1)93DWTC—DRAM Write Thermal Management Control Register (Device 1)94DRTC—DRAM Read Thermal Management Control Register (Device 1)95System Address Map97Memory Address Ranges97VGA and MDA Memory Space99PAM Memory Spaces100ISA Hole Memory Space100TSEG SMM Memory Space101IOAPIC Memory Space101System Bus Interrupt APIC Memory Space101High SMM Memory Space101AGP Aperture Space (Device 0 BAR)102AGP Memory and Prefetchable Memory102Hub Interface Subtractive Decode102AGP Memory Address Ranges102AGP DRAM Graphics Aperture103System Management Mode (SMM) Memory Range103SMM Space Definition104SMM Space Restrictions104I/O Address Space105Intel® MCH Decode Rules and Cross-Bridge Address Mapping105Hub Interface Decode Rules105AGP Interface Decode Rules106Functional Description107System Bus107Dynamic Bus Inversion107System Bus Interrupt Delivery108Upstream Interrupt Messages108System Memory Interface109Single Data Rate (SDR) SDRAM Interface Overview109Memory Organization and Configuration109Configuration Mechanism For DIMMs110Memory Address Translation and Decoding111DRAM Performance Description112Data Integrity (ECC)112AGP Interface Overview112AGP Target Operations112AGP Transaction Ordering114AGP Signal Levels1144x AGP Protocol114Fast Writes114AGP FRAME# Transactions on AGP115Power and Thermal Management117Processor Power State Control117Sleep State Control118Intel® MCH Clocking118Intel® MCH System Reset and Power Sequencing118Electrical Characteristics119Absolute Maximum Ratings119Power Characteristics119Signal Groups120DC Characteristics122Ballout and Package Information125Package Mechanical Information134Testability137XOR Test Mode Initialization137XOR Chains138Taille: 1,1 MoPages: 148Language: EnglishOuvrir le manuel