Manuais de utilizador para Intel 845

índice analítico

• Title Page

  1
• Contents

  3
• Revision History

  8
• Introduction

  11
  • Terminology and Notations

    11
  • Reference Documents

    13
  • Intel® 845 Chipset System Architecture

    14
  • Intel® 82845 MCH Overview

    14
    • System Bus Interface

      15
    • System Bus Error Checking

      15
    • System Memory Interface

      16
    • AGP Interface

      16
    • Hub Interface

      17
    • Intel® MCH Clocking

      17
    • System Interrupts

      18
    • Powerdown Flow

      18
• Signal Description

  19
  • System Bus Signals

    21
  • SDR SDRAM Interface Signals

    23
    • AGP Addressing Signals

      24
    • AGP Flow Control Signals

      25
• Register Description

  31
  • Register Terminology

    31
    • Standard PCI Bus Configuration Mechanism

      33
    • Routing Configuration Accesses

      33
  • I/O Mapped Registers

    34
    • CONF_ADDR—Configuration Address Register

      34
    • CONF_DATA—Configuration Data Register

      36
  • Memory-Mapped Register Space

    36
    • DRAMWIDTH—DRAM Width Register

      37
    • DQCMDSTR—Strength Control Register (SDQ and CMD Signal Groups)

      38
    • CKESTR—Strength Control Register (SCKE Signal Group)

      39
    • CSBSTR—Strength Control Register (SCS# Signal Group)

      40
    • CKSTR—Strength Control Register (Clock Signal Group)

      41
    • RCVENSTR—Strength Control Register (RCVENOUT Signal Group)

      42
  • Host-Hub Interface Bridge Device Registers (Device 0)

    43
    • VID—Vendor Identification Register (Device 0)

      45
    • DID—Device Identification Register (Device 0)

      45
    • PCICMD—PCI Command Register (Device 0)

      46
    • PCISTS—PCI Status Register (Device 0)

      47
    • RID—Revision Identification Register (Device 0)

      48
    • SUBC—Sub-Class Code Register (Device 0)

      48
    • BCC—Base Class Code Register (Device 0)

      48
    • MLT—Master Latency Timer Register (Device 0)

      49
    • HDR—Header Type Register (Device 0)

      49
    • APBASE—Aperture Base Configuration Register (Device 0)

      50
    • SVID—Subsystem Vendor Identification (Device 0)

      51
    • SID—Subsystem Identification (Device 0)

      51
    • CAPPTR—Capabilities Pointer (Device 0)

      51
    • AGPM—AGP Miscellaneous Configuration Register (Device 0)

      52
    • DRB[0:7]—DRAM Row Boundary Registers (Device 0)

      52
    • DRA—DRAM Row Attribute Registers (Device 0)

      53
    • DRT—DRAM Timing Register (Device 0)

      55
    • DRC—DRAM Controller Mode Register (Device 0)

      56
    • DERRSYN—DRAM Error Syndrome Register (Device 0)

      58
    • EAP—Error Address Pointer Register (Device 0)

      58
    • PAM[0:6]—Programmable Attribute Map Registers (Device 0)

      59
    • FDHC—Fixed DRAM Hole Control Register (Device 0)

      62
    • SMRAM—System Management RAM Control Register (Device 0)

      63
    • ESMRAMC—Extended System Mgmt RAM Control Register (Device 0)

      64
    • ACAPID—AGP Capability Identifier Register (Device 0)

      65
    • AGPSTAT—AGP Status Register (Device 0)

      66
    • AGPCMD—AGP Command Register (Device 0)

      67
    • AGPCTRL—AGP Control Register (Device 0)

      68
    • APSIZE—Aperture Size (Device 0)

      69
    • ATTBASE—Aperture Translation Table Base Register (Device 0)

      70
    • AMTT—AGP Interface Multi-Transaction Timer Register (Device 0)

      71
    • LPTT—AGP Low Priority Transaction Timer Register (Device 0)

      72
    • TOM—Top of Low Memory Register (Device 0)

      73
    • MCHCFG—MCH Configuration Register (Device 0)

      74
    • ERRSTS—Error Status Register (Device 0)

      75
    • ERRCMD—Error Command Register (Device 0)

      76
    • SMICMD—SMI Command Register (Device 0)

      78
    • SCICMD—SCI Command Register (Device 0)

      78
    • SKPD—Scratchpad Data Register (Device 0)

      79
    • CAPID—Product Specific Capability Identifier Register (Device 0)

      79
  • Bridge Registers (Device 1)

    80
    • VID1—Vendor Identification Register (Device 1)

      81
    • DID1—Device Identification Register (Device 1)

      81
    • PCICMD1—PCI-PCI Command Register (Device 1)

      82
    • PCISTS1—PCI-PCI Status Register (Device 1)

      83
    • RID1—Revision Identification Register (Device 1)

      84
    • SUBC1—Sub-Class Code Register (Device 1)

      84
    • BCC1—Base Class Code Register (Device 1)

      84
    • MLT1—Master Latency Timer Register (Device 1)

      85
    • HDR1—Header Type Register (Device 1)

      85
    • PBUSN1—Primary Bus Number Register (Device 1)

      85
    • SBUSN1—Secondary Bus Number Register (Device 1)

      86
    • SUBUSN1—Subordinate Bus Number Register (Device 1)

      86
    • SMLT1—Secondary Master Latency Timer Register (Device 1)

      87
    • IOBASE1—I/O Base Address Register (Device 1)

      88
    • IOLIMIT1—I/O Limit Address Register (Device 1)

      88
    • SSTS1—Secondary PCI-PCI Status Register (Device 1)

      89
    • MBASE1—Memory Base Address Register (Device 1)

      90
    • MLIMIT1—Memory Limit Address Register (Device 1)

      90
    • PMBASE1—Prefetchable Memory Base Address Register (Device 1)

      91
    • PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)

      91
    • BCTRL1—PCI-PCI Bridge Control Register (Device 1)

      92
    • ERRCMD1—Error Command Register (Device 1)

      93
    • DWTC—DRAM Write Thermal Management Control Register (Device 1)

      94
    • DRTC—DRAM Read Thermal Management Control Register (Device 1)

      95
• System Address Map

  97
  • Memory Address Ranges

    97
    • VGA and MDA Memory Space

      99
    • PAM Memory Spaces

      100
    • ISA Hole Memory Space

      100
    • TSEG SMM Memory Space

      101
    • IOAPIC Memory Space

      101
    • System Bus Interrupt APIC Memory Space

      101
    • High SMM Memory Space

      101
    • AGP Aperture Space (Device 0 BAR)

      102
    • AGP Memory and Prefetchable Memory

      102
    • Hub Interface Subtractive Decode

      102
  • AGP Memory Address Ranges

    102
    • AGP DRAM Graphics Aperture

      103
  • System Management Mode (SMM) Memory Range

    103
    • SMM Space Definition

      104
    • SMM Space Restrictions

      104
  • I/O Address Space

    105
  • Intel® MCH Decode Rules and Cross-Bridge Address Mapping

    105
    • Hub Interface Decode Rules

      105
    • AGP Interface Decode Rules

      106
• Functional Description

  107
  • System Bus

    107
    • Dynamic Bus Inversion

      107
    • System Bus Interrupt Delivery

      108
    • Upstream Interrupt Messages

      108
  • System Memory Interface

    109
    • Single Data Rate (SDR) SDRAM Interface Overview

      109
    • Memory Organization and Configuration

      109
      • Configuration Mechanism For DIMMs

        110
    • Memory Address Translation and Decoding

      111
    • DRAM Performance Description

      112
      • Data Integrity (ECC)

        112
  • AGP Interface Overview

    112
    • AGP Target Operations

      112
    • AGP Transaction Ordering

      114
    • AGP Signal Levels

      114
    • 4x AGP Protocol

      114
    • Fast Writes

      114
    • AGP FRAME# Transactions on AGP

      115
  • Power and Thermal Management

    117
    • Processor Power State Control

      117
    • Sleep State Control

      118
  • Intel® MCH Clocking

    118
  • Intel® MCH System Reset and Power Sequencing

    118
• Electrical Characteristics

  119
  • Absolute Maximum Ratings

    119
  • Power Characteristics

    119
  • Signal Groups

    120
  • DC Characteristics

    122
• Ballout and Package Information

  125
  • Package Mechanical Information

    134
• Testability

  137
  • XOR Test Mode Initialization

    137
  • XOR Chains

    138