Manuel D’Utilisation (80526KY7001M)Table des matièresProduct Features11. INTRODUCTION72. TERMINOLOGY82.1 S.E.C. CARTRIDGE TERMINOLOGY8Additional terms referred to in this and other related documentation:9State of Data9References93. ELECTRICAL SPECIFICATIONS10System Bus and VREF10Power and Ground Pins10Decoupling Guidelines123.3.1 VCC_CORE12LEVEL 2 CACHE DECOUPLING12SYSTEM BUS AGTL+ DECOUPLING12Clock Frequencies and System Bus Clock Ratios12MIXING PROCESSORS OF DIFFERENT FREQUENCIES14Voltage Identification14System Bus Unused Pins and Test Pins17System Bus Signal Groups17ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS18Access Port (TAP) Connection18Maximum Ratings19Processor DC Specifications19AGTL+ System Bus Specifications23System Bus AC Specifications25262626Table€12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3264344. Signal Quality344.1 Bus Clock Signal Quality Specifications344.2 AGTL+ Signal Quality Specifications354.2.2 AGTL+ Signal Quality Specifications354.2.3 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES354.2.3.1 Overshoot/Undershoot Magnitude364.2.3.2 Overshoot/Undershoot Pulse Duration364.2.3.3 Overshoot/Undershoot Activity Factor364.2.3.4 Determining if a System Meets the Overshoot/Undershoot Specifications36NOTES:384.3 Non-GTL+ Signal Quality Specifications384.3.1 2.5V Signal Overshoot/Undershoot Guidelines39Max Pulse Duration (nS)39NOTES:40404.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications404.3.3 Measuring BCLK Overshoot/Undershoot404.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION414.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE415. PROCESSOR FEATURES425.1 Low Power States and Clock Control42NORMAL STATE — STATE 142AUTO HALT POWER DOWN STATE — STATE 242STOP-GRANT STATE — STATE 343HALT/GRANT SNOOP STATE — STATE 443SLEEP STATE — STATE 544CLOCK CONTROL44System Management Bus (SMBus) Interface44PROCESSOR INFORMATION ROM45SCRATCH EEPROM49PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS49THERMAL SENSOR50THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS51THERMAL SENSOR REGISTERS52Thermal Reference Registers52Thermal Limit Registers52Status Register53Configuration Register53Conversion Rate Register53SMBus Device Addressing546. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS56Thermal Specifications56POWER DISSIPATION56NOTES:5758PLATE FLATNESS SPECIFICATION58Processor Thermal Analysis58THERMAL SOLUTION PERFORMANCE58THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE59NOTES:5959MEASUREMENTS FOR THERMAL SPECIFICATIONS59Plate Temperature Measurement597. MECHANICAL SPECIFICATIONS617.1 Weight657.2 Cartridge to Connector Mating Details657.3 Substrate Edge Finger Signal Listing678. INTEGRATION TOOLS778.1 In-Target Probe (ITP)778.1.1 PRIMARY FUNCTION778.1.2 DEBUG PORT CONNECTOR DESCRIPTION778.1.3 KEEP OUT CONCERNS788.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS788.1.5 DEBUG PORT SIGNAL DESCRIPTIONS788.1.6 DEBUG PORT SIGNAL NOTES818.1.6.1 General Signal Quality Notes818.1.6.2 Signal Note: DBRESET#818.1.6.3 Signal Note: TDO and TDI818.1.6.4 Signal Note: TCK and TMS828.1.7 Using the TAP to Communicate to the processor838.2 Logic Analyzer Interconnect (LAI) and Trace Capture Tool Considerations838.2.1 LAI and Trace Capture Tool System Design Considerations838.2.2 LAI and Trace Capture tool Mechanical Keep Outs839. BOXED PROCESSOR SPECIFICATIONS849.1 Introduction849.2 Mechanical Specifications849.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS869.2.2 BOXED PROCESSOR HEATSINK WEIGHT869.2.3 BOXED PROCESSOR RETENTION MECHANISM869.3 Thermal Specifications879.3.1 Boxed Processor Cooling Requirements879.3.2 Boxed Processor Passive Heatsink Performance879.3.2 Optional auxiliary fan attachment889.3.2.1 Clearance recommendations for auxiliary fan889.3.2.2 Fan power recommendations for auxiliary fan899.3.2.3 Thermal evaluation for auxiliary fan9010. APPENDIX9110.1 Alphabetical Signals Reference9110.1.1 A[35:03]# (I/O)9110.1.2 A20M# (I)9110.1.3 ADS# (I/O)9110.1.4 AERR# (I/O)9110.1.5 AP[1:0]# (I/O)9110.1.6 BCLK (I)9110.1.7 BERR# (I/O)9210.1.8 BINIT# (I/O)9210.1.9 BNR# (I/O)9210.1.10 BP[3:2]# (I/O)9210.1.11 BPM[1:0]# (I/O)9210.1.12 BPRI# (I)9210.1.13 BR0# (I/O), BR[3:1]# (I)9210.1.15 CORE_AN_SENSE (O)9310.1.16 D[63:00]# (I/O)9310.1.17 DBSY# (I/O)9410.1.18 DEFER# (I)9410.1.19 DEP[7:0]# (I/O)9410.1.20 DRDY# (I/O)9410.1.21 FERR# (O)9410.1.22 FLUSH# (I)9410.1.23 HIT# (I/O), HITM# (I/O)9410.1.24 HV_EN# (O)9410.1.25 IERR# (O)9410.1.26 IGNNE# (I)9510.1.27 INIT# (I)9510.1.28 INTR - see LINT[0]9510.1.29 LINT[1:0] (I)9510.1.30 LOCK# (I/O)9510.1.31 L2_SENSE9610.1.32 OCVR_EN (I)9610.1.33 OCVR_OK(O)9610.1.34 NMI - See LINT[1]9610.1.35 PICCLK (I)9610.1.36 PICD[1:0] (I/O)9610.1.37 PRDY# (O)9610.1.38 PREQ# (I)9610.1.39 PWREN[1:0] (I)9610.1.40 PWRGOOD (I)9697979797Figure€41. PWRGD Relationship at Power-On9710.1.41 REQ[4:0]# (I/O)9810.1.42 RESET# (I)9910.1.43 RP# (I/O)9910.1.44 RS[2:0]# (I)9910.1.45 RSP# (I)9910.1.46 SA[2:0] (I)9910.1.47 SELFSB0 (I) SELFSB1 (O)10010.1.48 SLP# (I)10110.1.49 SMBALERT# (O)10110.1.50 SMBCLK (I)10110.1.51 SMBDAT (I/O)10210.1.52 SMI# (I)10210.1.53 STPCLK# (I)10210.1.54 TCK (I)10210.1.55 TDI (I)10210.1.56 TDO (O)10210.1.57 TEST_2.5_[A23, A62, B27] (I)10210.1.58 THERMTRIP# (O)10210.1.59 TMS (I)10210.1.60 TRDY# (I)10310.1.61 TRST# (I)10310.1.62 VID_L2[4:0], VID_CORE[4:0] (O)10310.1.63 VIN_SENSE10310.1.64 WP (I)10310.2 Signal Summaries103Taille: 1,1 MoPages: 105Language: EnglishOuvrir le manuel
Manuel D’Utilisation (80526KY7002M)Table des matièresProduct Features11. INTRODUCTION72. TERMINOLOGY82.1 S.E.C. CARTRIDGE TERMINOLOGY8Additional terms referred to in this and other related documentation:9State of Data9References93. ELECTRICAL SPECIFICATIONS10System Bus and VREF10Power and Ground Pins10Decoupling Guidelines123.3.1 VCC_CORE12LEVEL 2 CACHE DECOUPLING12SYSTEM BUS AGTL+ DECOUPLING12Clock Frequencies and System Bus Clock Ratios12MIXING PROCESSORS OF DIFFERENT FREQUENCIES14Voltage Identification14System Bus Unused Pins and Test Pins17System Bus Signal Groups17ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS18Access Port (TAP) Connection18Maximum Ratings19Processor DC Specifications19AGTL+ System Bus Specifications23System Bus AC Specifications25262626Table€12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3264344. Signal Quality344.1 Bus Clock Signal Quality Specifications344.2 AGTL+ Signal Quality Specifications354.2.2 AGTL+ Signal Quality Specifications354.2.3 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES354.2.3.1 Overshoot/Undershoot Magnitude364.2.3.2 Overshoot/Undershoot Pulse Duration364.2.3.3 Overshoot/Undershoot Activity Factor364.2.3.4 Determining if a System Meets the Overshoot/Undershoot Specifications36NOTES:384.3 Non-GTL+ Signal Quality Specifications384.3.1 2.5V Signal Overshoot/Undershoot Guidelines39Max Pulse Duration (nS)39NOTES:40404.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications404.3.3 Measuring BCLK Overshoot/Undershoot404.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION414.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE415. PROCESSOR FEATURES425.1 Low Power States and Clock Control42NORMAL STATE — STATE 142AUTO HALT POWER DOWN STATE — STATE 242STOP-GRANT STATE — STATE 343HALT/GRANT SNOOP STATE — STATE 443SLEEP STATE — STATE 544CLOCK CONTROL44System Management Bus (SMBus) Interface44PROCESSOR INFORMATION ROM45SCRATCH EEPROM49PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS49THERMAL SENSOR50THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS51THERMAL SENSOR REGISTERS52Thermal Reference Registers52Thermal Limit Registers52Status Register53Configuration Register53Conversion Rate Register53SMBus Device Addressing546. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS56Thermal Specifications56POWER DISSIPATION56NOTES:5758PLATE FLATNESS SPECIFICATION58Processor Thermal Analysis58THERMAL SOLUTION PERFORMANCE58THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE59NOTES:5959MEASUREMENTS FOR THERMAL SPECIFICATIONS59Plate Temperature Measurement597. MECHANICAL SPECIFICATIONS617.1 Weight657.2 Cartridge to Connector Mating Details657.3 Substrate Edge Finger Signal Listing678. INTEGRATION TOOLS778.1 In-Target Probe (ITP)778.1.1 PRIMARY FUNCTION778.1.2 DEBUG PORT CONNECTOR DESCRIPTION778.1.3 KEEP OUT CONCERNS788.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS788.1.5 DEBUG PORT SIGNAL DESCRIPTIONS788.1.6 DEBUG PORT SIGNAL NOTES818.1.6.1 General Signal Quality Notes818.1.6.2 Signal Note: DBRESET#818.1.6.3 Signal Note: TDO and TDI818.1.6.4 Signal Note: TCK and TMS828.1.7 Using the TAP to Communicate to the processor838.2 Logic Analyzer Interconnect (LAI) and Trace Capture Tool Considerations838.2.1 LAI and Trace Capture Tool System Design Considerations838.2.2 LAI and Trace Capture tool Mechanical Keep Outs839. BOXED PROCESSOR SPECIFICATIONS849.1 Introduction849.2 Mechanical Specifications849.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS869.2.2 BOXED PROCESSOR HEATSINK WEIGHT869.2.3 BOXED PROCESSOR RETENTION MECHANISM869.3 Thermal Specifications879.3.1 Boxed Processor Cooling Requirements879.3.2 Boxed Processor Passive Heatsink Performance879.3.2 Optional auxiliary fan attachment889.3.2.1 Clearance recommendations for auxiliary fan889.3.2.2 Fan power recommendations for auxiliary fan899.3.2.3 Thermal evaluation for auxiliary fan9010. APPENDIX9110.1 Alphabetical Signals Reference9110.1.1 A[35:03]# (I/O)9110.1.2 A20M# (I)9110.1.3 ADS# (I/O)9110.1.4 AERR# (I/O)9110.1.5 AP[1:0]# (I/O)9110.1.6 BCLK (I)9110.1.7 BERR# (I/O)9210.1.8 BINIT# (I/O)9210.1.9 BNR# (I/O)9210.1.10 BP[3:2]# (I/O)9210.1.11 BPM[1:0]# (I/O)9210.1.12 BPRI# (I)9210.1.13 BR0# (I/O), BR[3:1]# (I)9210.1.15 CORE_AN_SENSE (O)9310.1.16 D[63:00]# (I/O)9310.1.17 DBSY# (I/O)9410.1.18 DEFER# (I)9410.1.19 DEP[7:0]# (I/O)9410.1.20 DRDY# (I/O)9410.1.21 FERR# (O)9410.1.22 FLUSH# (I)9410.1.23 HIT# (I/O), HITM# (I/O)9410.1.24 HV_EN# (O)9410.1.25 IERR# (O)9410.1.26 IGNNE# (I)9510.1.27 INIT# (I)9510.1.28 INTR - see LINT[0]9510.1.29 LINT[1:0] (I)9510.1.30 LOCK# (I/O)9510.1.31 L2_SENSE9610.1.32 OCVR_EN (I)9610.1.33 OCVR_OK(O)9610.1.34 NMI - See LINT[1]9610.1.35 PICCLK (I)9610.1.36 PICD[1:0] (I/O)9610.1.37 PRDY# (O)9610.1.38 PREQ# (I)9610.1.39 PWREN[1:0] (I)9610.1.40 PWRGOOD (I)9697979797Figure€41. PWRGD Relationship at Power-On9710.1.41 REQ[4:0]# (I/O)9810.1.42 RESET# (I)9910.1.43 RP# (I/O)9910.1.44 RS[2:0]# (I)9910.1.45 RSP# (I)9910.1.46 SA[2:0] (I)9910.1.47 SELFSB0 (I) SELFSB1 (O)10010.1.48 SLP# (I)10110.1.49 SMBALERT# (O)10110.1.50 SMBCLK (I)10110.1.51 SMBDAT (I/O)10210.1.52 SMI# (I)10210.1.53 STPCLK# (I)10210.1.54 TCK (I)10210.1.55 TDI (I)10210.1.56 TDO (O)10210.1.57 TEST_2.5_[A23, A62, B27] (I)10210.1.58 THERMTRIP# (O)10210.1.59 TMS (I)10210.1.60 TRDY# (I)10310.1.61 TRST# (I)10310.1.62 VID_L2[4:0], VID_CORE[4:0] (O)10310.1.63 VIN_SENSE10310.1.64 WP (I)10310.2 Signal Summaries103Taille: 1,1 MoPages: 105Language: EnglishOuvrir le manuel