Manuels d'utilisation pour Intel SE7520JR2

Table des matières

• Introduction

  19
• Chapter Outline

  19
• Server Board Use Disclaimer

  20
• Server Board Overview

  21
• Server Board SE7520JR2 SKU Availability

  21
• Server Board SE7520JR2 Feature Set

  21
• Functional Architecture

  26
• Processor Sub-system

  27
• Processor Voltage Regulators

  27
• Reset Configuration Logic

  27
• Processor Module Presence Detection

  27
• GTL2006

  27
• Common Enabling Kit (CEK) Design Support

  28
• Processor Support

  28
• 3.1.6.1 Processor Mis-population Detection

  29
• 3.1.6.2 Mixed Processor Steppings

  29
• 3.1.6.3 Mixed Processor Models

  29
• 3.1.6.4 Mixed Processor Families

  29
• 3.1.6.5 Mixed Processor Cache Sizes

  29
• 3.1.6.6 Jumperless Processor Speed Settings

  29
• 3.1.6.7 Microcode

  30
• 3.1.6.8 Processor Cache

  30
• 3.1.6.9 Hyper-Threading Technology

  30
• 3.1.6.10 Intel® SpeedStep® Technology

  30
• 3.1.6.11 EM64T Technology Support

  30
• Multiple Processor Initialization

  30
• CPU Thermal Sensors

  31
• Processor Thermal Control Sensor

  31
• Processor Thermal Trip Shutdown

  31
• Processor IERR

  31
• Intel® E7520 Chipset

  31
• Memory Controller Hub (MCH)

  32
• 3.2.1.1 Front Side Bus (FSB)

  32
• 3.2.1.2 MCH Memory Sub-System Overview

  32
• 3.2.1.3 PCI Express

  32
• 3.2.1.4 Hub Interface

  33
• PCI-X Hub (PXH)

  33
• 3.2.2.1 Full-height Riser Slot

  33
• 3.2.2.2 Low Profile Riser Slot

  33
• 3.2.2.3 I/OxAPIC Controller

  34
• 3.2.2.4 SMBus Interface

  34
• I/O Controller Hub (ICH5-R)

  34
• 3.2.3.1 PCI Interface

  34
• 3.2.3.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode)

  34
• 3.2.3.3 SATA Controller

  35
• 3.2.3.4 Low Pin Count (LPC) Interface

  35
• 3.2.3.6 Advanced Programmable Interrupt Controller (APIC)

  36
• 3.2.3.7 Universal Serial Bus (USB) Controller

  36
• 3.2.3.8 RTC

  36
• 3.2.3.9 General Purpose I/O (GPIO)

  36
• 3.2.3.10 Enhanced Power Management

  36
• 3.2.3.11 System Management Bus (SMBus 2.0)

  36
• Memory Sub-System

  37
• Memory Sizing

  37
• Memory Population

  38
• ECC Memory Initialization

  40
• Memory Test

  40
• Memory Monitoring

  41
• Memory RASUM Features

  42
• 3.3.6.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC)

  42
• 3.3.6.2 Integrated Memory Scrub Engine

  42
• 3.3.6.3 Retry on Uncorrectable Error

  43
• 3.3.6.4 Integrated Memory Initialization Engine

  43
• 3.3.6.5 DIMM Sparing Function

  44
• 3.3.6.6 Memory Mirroring

  45
• 3.3.6.7 Logging Memory RAS Information to the SEL

  47
• I/O Sub-System

  47
• PCI Subsystem

  47
• 3.4.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem

  48
• 3.4.1.2 P64-A and P64-B: 64-bit, 100MHz PCI Subsystem

  48
• 3.4.1.3 P64-Express: Dual x4 PCI Bus Segment

  48
• 3.4.1.4 PCI Riser Slots

  48
• 3.4.1.5 PCI Scan Order

  49
• 3.4.1.6 PCI Bus Numbering

  49
• 3.4.1.7 Device Number and IDSEL Mapping

  50
• 3.4.1.8 Resource Assignment

  52
• 3.4.1.9 Automatic IRQ Assignment

  52
• 3.4.1.10 Option ROM Support

  52
• 3.4.1.11 PCI APIs

  52
• Split Option ROM

  52
• Interrupt Routing

  52
• 3.4.3.1 Legacy Interrupt Routing

  52
• 3.4.3.2 APIC Interrupt Routing

  53
• 3.4.3.3 Legacy Interrupt Sources

  54
• 3.4.3.4 Serialized IRQ Support

  54
• 3.4.3.5 IRQ Scan for PCIIRQ

  55
• SCSI Support

  58
• 3.4.4.1 LSI* 53C1030 Dual Channel Ultra320 SCSI Controller

  58
• 3.4.4.2 Zero Channel RAID

  60
• IDE Support

  60
• 3.4.5.1 Ultra ATA/100

  61
• 3.4.5.2 IDE Initialization

  61
• SATA Support

  61
• 3.4.6.1 SATA RAID

  62
• 3.4.6.2 Intel® RAID Technology Option ROM

  62
• Video Support

  62
• 3.4.7.1 Video Modes

  62
• 3.4.7.2 Video Memory Interface

  63
• 3.4.7.3 Dual video

  64
• Network Interface Controller (NIC)

  64
• 3.4.8.1 NIC Connector and Status LEDs

  65
• USB 2.0 Support

  65
• 3.4.10 Super I/O Chip

  65
• 3.4.10.1 GPIOs

  65
• 3.4.10.2 Serial Ports

  67
• 3.4.10.3 Removable Media Drives

  69
• 3.4.10.4 Floppy Disk Support

  69
• 3.4.10.5 Keyboard and Mouse Support

  69
• 3.4.10.6 Wake-up Control

  69
• 3.4.11 BIOS Flash

  69
• Configuration and Initialization

  70
• Memory Space

  70
• 3.5.1.1 DOS Compatibility Region

  71
• 3.5.1.2 Extended Memory

  73
• 3.5.1.3 Memory Shadowing

  74
• 3.5.1.4 System Management Mode Handling

  75
• I/O Map

  76
• Accessing Configuration Space

  78
• 3.5.3.1 CONFIG_ADDRESS Register

  79
• Clock Generation and Distribution

  79
• System BIOS

  80
• BIOS Identification String

  80
• Flash Architecture and Flash Update Utility

  81
• BIOS Power On Self Test (POST)

  81
• User Interface

  81
• 4.3.1.1 System Activity Window

  82
• 4.3.1.2 Splash Screen/Diagnostic Window

  82
• 4.3.1.3 POST Activity Window

  83
• BIOS Boot Popup Menu

  83
• BIOS Setup Utility

  84
• Localization

  84
• Entering BIOS Setup

  85
• 4.4.2.1 Main Menu

  85
• 4.4.2.2 Advanced Menu

  86
• 4.4.2.3 Boot Menu

  95
• 4.4.2.4 Security Menu

  98
• 4.4.2.5 Server Menu

  99
• 4.4.2.6 Exit Menu

  102
• Rolling BIOS and On-line Updates

  102
• Flash Update Utility

  103
• 4.5.1.1 Flash BIOS

  103
• 4.5.1.2 User Binary Area

  103
• 4.5.1.3 Recovery Mode

  103
• 4.5.1.4 BIOS Recovery

  104
• .Configuration Reset

  104
• OEM Binary

  105
• Security

  105
• Operating Model

  106
• Password Clear Jumper

  108
• Extensible Firmware Interface (EFI)

  108
• EFI Shell

  108
• Operating System Boot, Sleep, and Wake

  108
• Microsoft* Windows* Compatibility

  108
• Advanced Configuration and Power Interface (ACPI)

  109
• 4.9.2.1 Sleep and Wake Functionality

  109
• 4.9.2.2 Power Switch Off to On

  110
• 4.9.2.3 On to Off (OS absent)

  110
• 4.9.2.4 On to Off (OS present)

  110
• 4.9.2.5 On to Sleep (ACPI)

  110
• 4.9.2.6 Sleep to On (ACPI)

  111
• 4.9.2.7 System Sleep States

  111
• PXE BIOS Support

  112
• Console Redirection

  112
• Platform Management

  113
• Platform Management Architecture Overview

  115
• 5V Standby

  116
• IPMI Messaging, Commands, and Abstractions xxx

  116
• IPMI ‘Sensor Model’

  117
• Private Management Busses

  118
• Management Controllers

  118
• On-Board Platform Management Features and Functionality

  121
• Server Management I2C Buses

  122
• Power Control Interfaces

  122
• External Interface to the mBMC

  122
• mBMC Hardware Architecture

  123
• Power Supply Interface Signals

  124
• Power Control Sources

  126
• Power-up Sequence

  126
• Power-down Sequence

  126
• System Reset Control

  126
• 5.3.5.1 Reset Signal Output

  126
• 5.3.5.2 Reset Control Sources

  127
• 5.3.5.3 Control Panel System Reset

  127
• 5.3.5.4 Control Panel Indicators

  128
• 5.3.5.5 Control Panel Inputs

  129
• Secure Mode Operation

  131
• Baseboard Fan Control

  131
• mBMC Peripheral SMBus

  131
• Watchdog Timer

  131
• 5.3.10 System Event Log (SEL)

  131
• 5.3.10.1 SEL Erasure

  132
• 5.3.10.2 Timestamp Clock

  132
• 5.3.11 Sensor Data Record (SDR) Repository

  132
• 5.3.11.1 Initialization Agent

  132
• 5.3.12 Field Replaceable Unit (FRU) Inventory Devices

  133
• 5.3.12.1 mBMC FRU Inventory Area Format

  133
• 5.3.13 NMI Generation

  133
• SMI Generation

  133
• Event Message Reception

  133
• mBMC Self Test

  134
• 5.3.17 Messaging Interfaces

  134
• 5.3.17.1 Channel Management

  134
• 5.3.17.2 User Model

  134
• 5.3.17.3 Request/Response Protocol

  134
• 5.3.17.4 Host to mBMC Communication Interface

  134
• 5.3.17.5 LAN Interface

  135
• 5.3.18 Event Filtering and Alerting

  136
• 5.3.18.1 Platform Event Filtering (PEF)

  136
• 5.3.18.2 Alert over LAN

  137
• 5.3.19 mBMC Sensor Support

  137
• IMM BMC Sensor Support

  142
• Wired For Management (WFM)

  148
• Vital Product Data (VPD)

  148
• System Management BIOS (SMBIOS)

  148
• Error Reporting and Handling

  149
• Fault Resilient Booting (FRB)

  149
• FRB1 – BSP Self-Test Failures

  149
• FRB2 – BSP POST Failures

  149
• FRB3 – BSP Reset Failures

  150
• AP Failures

  151
• Treatment of Failed Processors

  151
• Memory Error Handling in RAS Mode

  152
• Memory Error Handling in non-RAS Mode

  153
• DIMM Enabling

  154
• Single-bit ECC Error Throttling Prevention

  154
• Error Logging

  155
• 6.2.1.1 PCI Bus Error

  155
• 6.2.1.2 Processor Bus Error

  155
• 6.2.1.3 Memory Bus Error

  156
• 6.2.1.4 System Limit Error

  156
• 6.2.1.5 Processor Failure

  156
• 6.2.1.6 Boot Event

  156
• Error Messages and Error Codes

  156
• POST Error Messages

  156
• POST Error Codes

  162
• BIOS Generated POST Error Beep Codes

  165
• Boot Block Error Beep Codes

  166
• BMC Generated Beep Codes (Professional/Advanced only)

  166
• Checkpoints

  167
• System ROM BIOS POST Task Test Point (Port 80h Code)

  167
• Diagnostic LEDs

  167
• POST Code Checkpoints

  168
• Bootblock Initialization Code Checkpoints

  170
• Bootblock Recovery Code Checkpoint

  171
• DIM Code Checkpoints

  172
• ACPI Runtime Checkpoints

  173
• POST Progress FIFO (Professional / Advanced only)

  173
• Memory Error Codes

  173
• Light Guided Diagnostics

  174
• Connectors and Jumper Blocks

  175
• Power Connectors

  175
• Riser Slots

  176
• Low Profile PCI-X Riser Slot

  176
• Full Height PCI-X Riser Slot

  179
• System Management Headers

  184
• Intel® Management Module Connector

  184
• ICMB Header

  187
• IPMB Header

  187
• OEM RMC Connector (J3B2)

  189
• Control Panel Connectors

  189
• I/O Connectors

  192
• VGA Connector

  192
• NIC Connectors

  193
• SCSI Connectors

  193
• ATA-100 Connector

  194
• SATA Connectors

  195
• Floppy Controller Connector

  195
• Serial Port Connectors

  196
• Keyboard and Mouse Connector

  197
• USB Connector

  197
• Fan Headers

  198
• Misc. Headers and Connectors

  200
• Chassis Intrusion Header

  200
• Hard Drive Activity LED Header

  200
• Jumper Blocks

  201
• Design and Environmental Specifications

  202
• Server Board SE7520JR2 Design Specification

  202
• Power Supply Requirements

  202
• Output Connectors

  202
• Grounding

  205
• Remote Sense

  206
• Standby Outputs

  206
• Voltage Regulation

  207
• Dynamic Loading

  207
• Capacitive Loading

  208
• Closed Loop Stability

  208
• Common Mode Noise

  208
• Ripple / Noise

  208
• Soft Starting

  209
• Zero Load Stability Requirements

  209
• Timing Requirements

  209
• Residual Voltage Immunity in Standby Mode

  211
• Product Regulatory Compliance

  212
• Product Safety Compliance

  212
• Product EMC Compliance – Class A Compliance

  212
• Certifications / Registrations / Declarations

  213
• Product Regulatory Compliance Markings

  213
• Electromagnetic Compatibility Notices

  214
• FCC (USA)

  214
• Industry Canada (ICES-003)

  214
• Europe (CE Declaration of Conformity)

  215
• Taiwan Declaration of Conformity (BSMI)

  215
• Korean Compliance (RRL)

  215
• Miscellaneous Board Information

  216
• Updating the System Software

  216
• Programming FRU and SDR Data

  216
• Clearing CMOS

  217
• CMOS Clear Using J1H2 Jumper Block

  217
• CMOS Clear using Control Panel

  217
• BIOS Recovery Operation

  218
• Appendix A: Integration and Usage Tips

  221
• Glossary

  222
• Reference Documents

  225
• Figure 1. SE7520JR2 Board Layout

  23
• Figure 2. Server Board Dimensions

  25
• Figure 3. Server Board SE7520JR2 Block Diagram

  26
• Figure 4. CEK Processor Mounting

  28
• Figure 5. Identifying Banks of Memory

  38
• Figure 6. Four DIMM Memory Mirror Configuration

  45
• Figure 7. Six DIMM Memory Mirror Configuration (DDR2 Only)

  46
• Figure 8. Interrupt Routing Diagram (ICH5-R Internal)

  55
• Figure 9. Interrupt Routing Diagram

  56
• Figure 10. PCI Interrupt Mapping Diagram

  57
• Figure 11. PCI Interrupt Mapping Diagram for 2U Active Riser Card

  57
• Figure 12. Serial Port Mux Logic

  68
• Figure 13. RJ45 Serial B Port Jumper Block Location and Setting

  68
• Figure 14. Intel® Xeon™ Processor Memory Address Space

  70
• Figure 15. DOS Compatibility Region

  71
• Figure 16. Extended Memory Map

  73
• Figure 17. BIOS Identification String

  80
• Figure 18. POST Console Interface

  82
• Figure 19. On-Board Platform Management Architecture

  115
• Figure 20. mBMC in a Server Management System

  121
• Figure 21. External Interfaces to mBMC

  123
• Figure 22. mBMC Block Diagram

  124
• Figure 23. Power Supply Control Signals

  125
• Figure 24. Location of Diagnostic LEDs on Baseboard

  168
• Figure 25. 34-Pin SSI Compliant Control Panel Header

  192
• Figure 26. System Configuration (J1H2) Jumper Block Settings

  201
• Figure 27. Power Harness Specification Drawing

  203
• Figure 28. Output Voltage Timing

  210
• Figure 29. Turn On/Off Timing (Power Supply Signals)

  211
• Table 1: Baseboard Layout Reference

  24
• Table 2: Processor Support Matrix

  28
• Table 3: Supported DDR-266 DIMM Populations

  39
• Table 4: Supported DDR-333 DIMM Populations

  39
• Table 5: Supported DDR2-400 DIMM Populations

  40
• Table 6: Memory Monitoring Support by Server Management Level

  41
• Table 7: PCI Bus Segment Characteristics

  48
• Table 8: PCI Configuration IDs and Device Numbers

  51
• Table 9: PCI Interrupt Routing/Sharing

  53
• Table 10: Interrupt Definitions

  54
• Table 11: Video Modes

  63
• Table 12: Video Memory Interface

  63
• Table 13: Super I/O GPIO Usage Table

  65
• Table 14: Serial A Header Pin-out

  67
• Table 15: SMM Space Table

  75
• Table 16: I/O Map

  76
• Table 17: Sample BIOS Popup Menu

  84
• Table 18: BIOS Setup Keyboard Command Bar Options

  84
• Table 19: BIOS Setup, Main Menu Options

  85
• Table 20: BIOS Setup, Advanced Menu Options

  86
• Table 21: BIOS Setup, Processor Configuration Sub-menu Options

  87
• Table 22: BIOS Setup IDE Configuration Menu Options

  88
• Table 23: Mixed P-ATA-S-ATA Configuration with only Primary P-ATA

  89
• Table 24: BIOS Setup, IDE Device Configuration Sub-menu Selections

  90
• Table 25: BIOS Setup, Floppy Configuration Sub-menu Selections

  91
• Table 26: BIOS Setup, Super I/O Configuration Sub-menu

  91
• Table 27: BIOS Setup, USB Configuration Sub-menu Selections

  92
• Table 28: BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections

  92
• Table 29: BIOS Setup, PCI Configuration Sub-menu Selections

  93
• Table 30: BIOS Setup, Memory Configuration Sub-menu Selections

  94
• Table 31: BIOS Setup, Boot Menu Selections

  95
• Table 32: BIOS Setup, Boot Settings Configuration Sub-menu Selections

  96
• Table 33: BIOS Setup, Boot Device Priority Sub-menu Selections

  97
• Table 34: BIOS Setup, Hard Disk Drive Sub-Menu Selections

  97
• Table 35: BIOS Setup, Removable Drives Sub-menu Selections

  97
• Table 36: BIOS Setup, CD/DVD Drives Sub-menu Selections

  97
• Table 37: BIOS Setup, Security Menu Options

  98
• Table 38: BIOS Setup, Server Menu Selections

  99
• Table 39: BIOS Setup, System Management Sub-menu Selections

  100
• Table 40: BIOS Setup, Serial Console Features Sub-menu Selections

  101
• Table 41: BIOS Setup, Event Log Configuration Sub-menu Selections

  101
• Table 42: BIOS Setup, Exit Menu Selections

  102
• Table 43: Security Features Operating Model

  106
• Table 44: Supported Wake Events

  111
• Table 45: Suppoted Management Features by Tier

  113
• Table 46: Server Management I2C Bus ID Assignments

  122
• Table 47: Power Control Initiators

  126
• Table 48: System Reset Sources and Actions

  127
• Table 49: SSI Power LED Operation

  128
• Table 50: Fault / Status LED

  129
• Table 51: Chassis ID LED

  129
• Table 52: Suported Channel Assignments

  134
• Table 53: LAN Channel Capacity

  135
• Table 54: PEF Action Priorities

  137
• Table 55: Platform Sensors for On-Board Platform Instrumentation

  138
• Table 56. Platform Sensors for Intel Management Modules - Professional and Advanced

  142
• Table 57: Memory Error Handling mBMC vs Sahalee

  153
• Table 58: Memory Error Handling in non-RAS mode

  154
• Table 59: Memory BIOS Messages

  156
• Table 60: Boot BIOS Messages

  157
• Table 61: Storage Device BIOS Messages

  157
• Table 62: Virus Related BIOS Messages

  160
• Table 63: System Configuration BIOS Messages

  160
• Table 64: CMOS BIOS Messages

  161
• Table 65: Miscellaneous BIOS Messages

  161
• Table 66: USB BIOS Error Messages

  161
• Table 67: SMBIOS BIOS Error Messages

  162
• Table 68: Error Codes and Messages

  162
• Table 69: Error Codes Sent to the Management Module

  164
• Table 70: BIOS Generated Beep Codes

  165
• Table 71: Troubleshooting BIOS Beep Codes

  166
• Table 72: Boot Block Error Beep Codes

  166
• Table 73: BMC Beep Code

  167
• Table 74: POST Progress Code LED Example

  167
• Table 75: POST Code Checkpoints

  168
• Table 76: Bootblock Initialization Code Checkpoints

  170
• Table 77: Bootblock Recovery Code Checkpoint

  171
• Table 78: DIM Code Checkpoints

  172
• Table 79: ACPI Runtime Checkpoints

  173
• Table 80: Memory Error Codes

  173
• Table 81: Power Connector Pin-out

  175
• Table 82: 12V Power Connector (J4J1)

  175
• Table 83: Power Supply Signal Connector (J1G1)

  176
• Table 84: IDE Power Connector Pinout (U2E1)

  176
• Table 85: Low Profile Riser Slot Pinout

  176
• Table 86: Full-height Riser Slot Pinout

  180
• Table 87: IMM Connector Pinout (J1C1)

  184
• Table 88: ICMB Header Pin-out (J1D1)

  187
• Table 89: IPMB Connector Pin-out (J3F1)

  188
• Table 90: OEM RMC Connector Pinout (J3B2)

  189
• Table 91: 100-Pin Flex Cable Connector Pin-out (For Intel Chassis w/Backplane) (J2J1)

  189
• Table 92: 50-Pin Control Panel Connector (Intel Chassis w/No Backplane) (J1J2)

  190
• Table 93: Control Panel SSI Standard 34-Pin Header Pin-out

  191
• Table 94: VGA Connector Pin-out

  192
• Table 95: RJ-45 10/100/1000 NIC Connector Pin-out

  193
• Table 96: Internal/External 68-pin VHDCI SCSI Connector Pin-out

  193
• Table 97: ATA-100 40-pin Connector Pin-out (J3K1)

  194
• Table 98: SATA Connector Pin-out (J1H1 and J1H5)

  195
• Table 99: Legacy 34-pin Floppy Drive Connector Pin-out (J3K2)

  196
• Table 100: External RJ-45 Serial B Port Pin-out

  196
• Table 101: Internal 9-pin Serial A Header Pin-out (J1A3)

  196
• Table 102: Stacked PS/2 Keyboard and Mouse Port Pin-out

  197
• Table 103: External USB Connector Pin-out

  197
• Table 104: Internal 1x10 USB Connector Pin-out (J1F1)

  198
• Table 105: Internal 2x5 USB Connector (J1G1)

  198
• Table 106: CPU1/CPU2 Fan Connector Pin-out (J5F2, J7F1)

  199
• Table 107: Intel Server Chassis Fan Header Pin-out (J3K6)

  199
• Table 108: 3-Pin Fan Speed Controlled Fan Header (J3K3)

  200
• Table 109: Chassis Intrusion Header (J1A1)

  200
• Table 110: Hard Drive Activity LED Header(J1A2)

  200
• Table 111: Jumper Block Definitions

  201
• Table 112: Board Design Specifications

  202
• Table 113: P1 Main Power Connector

  204
• Table 114: P2 Processor Power Connector

  204
• Table 115: P3 Baseboard Signal Connector

  205
• Table 116: Peripheral Power Connectors

  205
• Table 117: P7 Hard Drive Power Connector

  205
• Table 118: Voltage Regulation Limits

  207
• Table 119: Transient Load Requirements

  207
• Table 120: Capacitve Loading Conditions

  208
• Table 121: Ripple and Noise

  208
• Table 122: Output Voltage Timing

  209
• Table 123: Turn On/Off Timing

  210
• Product Certification Markings

  213