Справочник ПользователяСодержаниеIntroduction19Chapter Outline19Server Board Use Disclaimer20Server Board Overview21Server Board SE7520JR2 SKU Availability21Server Board SE7520JR2 Feature Set21Functional Architecture26Processor Sub-system27Processor Voltage Regulators27Reset Configuration Logic27Processor Module Presence Detection27GTL200627Common Enabling Kit (CEK) Design Support28Processor Support283.1.6.1 Processor Mis-population Detection293.1.6.2 Mixed Processor Steppings293.1.6.3 Mixed Processor Models293.1.6.4 Mixed Processor Families293.1.6.5 Mixed Processor Cache Sizes293.1.6.6 Jumperless Processor Speed Settings293.1.6.7 Microcode303.1.6.8 Processor Cache303.1.6.9 Hyper-Threading Technology303.1.6.10 Intel® SpeedStep® Technology303.1.6.11 EM64T Technology Support30Multiple Processor Initialization30CPU Thermal Sensors31Processor Thermal Control Sensor31Processor Thermal Trip Shutdown31Processor IERR31Intel® E7520 Chipset31Memory Controller Hub (MCH)323.2.1.1 Front Side Bus (FSB)323.2.1.2 MCH Memory Sub-System Overview323.2.1.3 PCI Express323.2.1.4 Hub Interface33PCI-X Hub (PXH)333.2.2.1 Full-height Riser Slot333.2.2.2 Low Profile Riser Slot333.2.2.3 I/OxAPIC Controller343.2.2.4 SMBus Interface34I/O Controller Hub (ICH5-R)343.2.3.1 PCI Interface343.2.3.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode)343.2.3.3 SATA Controller353.2.3.4 Low Pin Count (LPC) Interface353.2.3.6 Advanced Programmable Interrupt Controller (APIC)363.2.3.7 Universal Serial Bus (USB) Controller363.2.3.8 RTC363.2.3.9 General Purpose I/O (GPIO)363.2.3.10 Enhanced Power Management363.2.3.11 System Management Bus (SMBus 2.0)36Memory Sub-System37Memory Sizing37Memory Population38ECC Memory Initialization40Memory Test40Memory Monitoring41Memory RASUM Features423.3.6.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC)423.3.6.2 Integrated Memory Scrub Engine423.3.6.3 Retry on Uncorrectable Error433.3.6.4 Integrated Memory Initialization Engine433.3.6.5 DIMM Sparing Function443.3.6.6 Memory Mirroring453.3.6.7 Logging Memory RAS Information to the SEL47I/O Sub-System47PCI Subsystem473.4.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem483.4.1.2 P64-A and P64-B: 64-bit, 100MHz PCI Subsystem483.4.1.3 P64-Express: Dual x4 PCI Bus Segment483.4.1.4 PCI Riser Slots483.4.1.5 PCI Scan Order493.4.1.6 PCI Bus Numbering493.4.1.7 Device Number and IDSEL Mapping503.4.1.8 Resource Assignment523.4.1.9 Automatic IRQ Assignment523.4.1.10 Option ROM Support523.4.1.11 PCI APIs52Split Option ROM52Interrupt Routing523.4.3.1 Legacy Interrupt Routing523.4.3.2 APIC Interrupt Routing533.4.3.3 Legacy Interrupt Sources543.4.3.4 Serialized IRQ Support543.4.3.5 IRQ Scan for PCIIRQ55SCSI Support583.4.4.1 LSI* 53C1030 Dual Channel Ultra320 SCSI Controller583.4.4.2 Zero Channel RAID60IDE Support603.4.5.1 Ultra ATA/100613.4.5.2 IDE Initialization61SATA Support613.4.6.1 SATA RAID623.4.6.2 Intel® RAID Technology Option ROM62Video Support623.4.7.1 Video Modes623.4.7.2 Video Memory Interface633.4.7.3 Dual video64Network Interface Controller (NIC)643.4.8.1 NIC Connector and Status LEDs65USB 2.0 Support653.4.10 Super I/O Chip653.4.10.1 GPIOs653.4.10.2 Serial Ports673.4.10.3 Removable Media Drives693.4.10.4 Floppy Disk Support693.4.10.5 Keyboard and Mouse Support693.4.10.6 Wake-up Control693.4.11 BIOS Flash69Configuration and Initialization70Memory Space703.5.1.1 DOS Compatibility Region713.5.1.2 Extended Memory733.5.1.3 Memory Shadowing743.5.1.4 System Management Mode Handling75I/O Map76Accessing Configuration Space783.5.3.1 CONFIG_ADDRESS Register79Clock Generation and Distribution79System BIOS80BIOS Identification String80Flash Architecture and Flash Update Utility81BIOS Power On Self Test (POST)81User Interface814.3.1.1 System Activity Window824.3.1.2 Splash Screen/Diagnostic Window824.3.1.3 POST Activity Window83BIOS Boot Popup Menu83BIOS Setup Utility84Localization84Entering BIOS Setup854.4.2.1 Main Menu854.4.2.2 Advanced Menu864.4.2.3 Boot Menu954.4.2.4 Security Menu984.4.2.5 Server Menu994.4.2.6 Exit Menu102Rolling BIOS and On-line Updates102Flash Update Utility1034.5.1.1 Flash BIOS1034.5.1.2 User Binary Area1034.5.1.3 Recovery Mode1034.5.1.4 BIOS Recovery104.Configuration Reset104OEM Binary105Security105Operating Model106Password Clear Jumper108Extensible Firmware Interface (EFI)108EFI Shell108Operating System Boot, Sleep, and Wake108Microsoft* Windows* Compatibility108Advanced Configuration and Power Interface (ACPI)1094.9.2.1 Sleep and Wake Functionality1094.9.2.2 Power Switch Off to On1104.9.2.3 On to Off (OS absent)1104.9.2.4 On to Off (OS present)1104.9.2.5 On to Sleep (ACPI)1104.9.2.6 Sleep to On (ACPI)1114.9.2.7 System Sleep States111PXE BIOS Support112Console Redirection112Platform Management113Platform Management Architecture Overview1155V Standby116IPMI Messaging, Commands, and Abstractions xxx116IPMI ‘Sensor Model’117Private Management Busses118Management Controllers118On-Board Platform Management Features and Functionality121Server Management I2C Buses122Power Control Interfaces122External Interface to the mBMC122mBMC Hardware Architecture123Power Supply Interface Signals124Power Control Sources126Power-up Sequence126Power-down Sequence126System Reset Control1265.3.5.1 Reset Signal Output1265.3.5.2 Reset Control Sources1275.3.5.3 Control Panel System Reset1275.3.5.4 Control Panel Indicators1285.3.5.5 Control Panel Inputs129Secure Mode Operation131Baseboard Fan Control131mBMC Peripheral SMBus131Watchdog Timer1315.3.10 System Event Log (SEL)1315.3.10.1 SEL Erasure1325.3.10.2 Timestamp Clock1325.3.11 Sensor Data Record (SDR) Repository1325.3.11.1 Initialization Agent1325.3.12 Field Replaceable Unit (FRU) Inventory Devices1335.3.12.1 mBMC FRU Inventory Area Format1335.3.13 NMI Generation133SMI Generation133Event Message Reception133mBMC Self Test1345.3.17 Messaging Interfaces1345.3.17.1 Channel Management1345.3.17.2 User Model1345.3.17.3 Request/Response Protocol1345.3.17.4 Host to mBMC Communication Interface1345.3.17.5 LAN Interface1355.3.18 Event Filtering and Alerting1365.3.18.1 Platform Event Filtering (PEF)1365.3.18.2 Alert over LAN1375.3.19 mBMC Sensor Support137IMM BMC Sensor Support142Wired For Management (WFM)148Vital Product Data (VPD)148System Management BIOS (SMBIOS)148Error Reporting and Handling149Fault Resilient Booting (FRB)149FRB1 – BSP Self-Test Failures149FRB2 – BSP POST Failures149FRB3 – BSP Reset Failures150AP Failures151Treatment of Failed Processors151Memory Error Handling in RAS Mode152Memory Error Handling in non-RAS Mode153DIMM Enabling154Single-bit ECC Error Throttling Prevention154Error Logging1556.2.1.1 PCI Bus Error1556.2.1.2 Processor Bus Error1556.2.1.3 Memory Bus Error1566.2.1.4 System Limit Error1566.2.1.5 Processor Failure1566.2.1.6 Boot Event156Error Messages and Error Codes156POST Error Messages156POST Error Codes162BIOS Generated POST Error Beep Codes165Boot Block Error Beep Codes166BMC Generated Beep Codes (Professional/Advanced only)166Checkpoints167System ROM BIOS POST Task Test Point (Port 80h Code)167Diagnostic LEDs167POST Code Checkpoints168Bootblock Initialization Code Checkpoints170Bootblock Recovery Code Checkpoint171DIM Code Checkpoints172ACPI Runtime Checkpoints173POST Progress FIFO (Professional / Advanced only)173Memory Error Codes173Light Guided Diagnostics174Connectors and Jumper Blocks175Power Connectors175Riser Slots176Low Profile PCI-X Riser Slot176Full Height PCI-X Riser Slot179System Management Headers184Intel® Management Module Connector184ICMB Header187IPMB Header187OEM RMC Connector (J3B2)189Control Panel Connectors189I/O Connectors192VGA Connector192NIC Connectors193SCSI Connectors193ATA-100 Connector194SATA Connectors195Floppy Controller Connector195Serial Port Connectors196Keyboard and Mouse Connector197USB Connector197Fan Headers198Misc. Headers and Connectors200Chassis Intrusion Header200Hard Drive Activity LED Header200Jumper Blocks201Design and Environmental Specifications202Server Board SE7520JR2 Design Specification202Power Supply Requirements202Output Connectors202Grounding205Remote Sense206Standby Outputs206Voltage Regulation207Dynamic Loading207Capacitive Loading208Closed Loop Stability208Common Mode Noise208Ripple / Noise208Soft Starting209Zero Load Stability Requirements209Timing Requirements209Residual Voltage Immunity in Standby Mode211Product Regulatory Compliance212Product Safety Compliance212Product EMC Compliance – Class A Compliance212Certifications / Registrations / Declarations213Product Regulatory Compliance Markings213Electromagnetic Compatibility Notices214FCC (USA)214Industry Canada (ICES-003)214Europe (CE Declaration of Conformity)215Taiwan Declaration of Conformity (BSMI)215Korean Compliance (RRL)215Miscellaneous Board Information216Updating the System Software216Programming FRU and SDR Data216Clearing CMOS217CMOS Clear Using J1H2 Jumper Block217CMOS Clear using Control Panel217BIOS Recovery Operation218Appendix A: Integration and Usage Tips221Glossary222Reference Documents225Figure 1. SE7520JR2 Board Layout23Figure 2. Server Board Dimensions25Figure 3. Server Board SE7520JR2 Block Diagram26Figure 4. CEK Processor Mounting28Figure 5. Identifying Banks of Memory38Figure 6. Four DIMM Memory Mirror Configuration45Figure 7. Six DIMM Memory Mirror Configuration (DDR2 Only)46Figure 8. Interrupt Routing Diagram (ICH5-R Internal)55Figure 9. Interrupt Routing Diagram56Figure 10. PCI Interrupt Mapping Diagram57Figure 11. PCI Interrupt Mapping Diagram for 2U Active Riser Card57Figure 12. Serial Port Mux Logic68Figure 13. RJ45 Serial B Port Jumper Block Location and Setting68Figure 14. Intel® Xeon™ Processor Memory Address Space70Figure 15. DOS Compatibility Region71Figure 16. Extended Memory Map73Figure 17. BIOS Identification String80Figure 18. POST Console Interface82Figure 19. On-Board Platform Management Architecture115Figure 20. mBMC in a Server Management System121Figure 21. External Interfaces to mBMC123Figure 22. mBMC Block Diagram124Figure 23. Power Supply Control Signals125Figure 24. Location of Diagnostic LEDs on Baseboard168Figure 25. 34-Pin SSI Compliant Control Panel Header192Figure 26. System Configuration (J1H2) Jumper Block Settings201Figure 27. Power Harness Specification Drawing203Figure 28. Output Voltage Timing210Figure 29. Turn On/Off Timing (Power Supply Signals)211Table 1: Baseboard Layout Reference24Table 2: Processor Support Matrix28Table 3: Supported DDR-266 DIMM Populations39Table 4: Supported DDR-333 DIMM Populations39Table 5: Supported DDR2-400 DIMM Populations40Table 6: Memory Monitoring Support by Server Management Level41Table 7: PCI Bus Segment Characteristics48Table 8: PCI Configuration IDs and Device Numbers51Table 9: PCI Interrupt Routing/Sharing53Table 10: Interrupt Definitions54Table 11: Video Modes63Table 12: Video Memory Interface63Table 13: Super I/O GPIO Usage Table65Table 14: Serial A Header Pin-out67Table 15: SMM Space Table75Table 16: I/O Map76Table 17: Sample BIOS Popup Menu84Table 18: BIOS Setup Keyboard Command Bar Options84Table 19: BIOS Setup, Main Menu Options85Table 20: BIOS Setup, Advanced Menu Options86Table 21: BIOS Setup, Processor Configuration Sub-menu Options87Table 22: BIOS Setup IDE Configuration Menu Options88Table 23: Mixed P-ATA-S-ATA Configuration with only Primary P-ATA89Table 24: BIOS Setup, IDE Device Configuration Sub-menu Selections90Table 25: BIOS Setup, Floppy Configuration Sub-menu Selections91Table 26: BIOS Setup, Super I/O Configuration Sub-menu91Table 27: BIOS Setup, USB Configuration Sub-menu Selections92Table 28: BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections92Table 29: BIOS Setup, PCI Configuration Sub-menu Selections93Table 30: BIOS Setup, Memory Configuration Sub-menu Selections94Table 31: BIOS Setup, Boot Menu Selections95Table 32: BIOS Setup, Boot Settings Configuration Sub-menu Selections96Table 33: BIOS Setup, Boot Device Priority Sub-menu Selections97Table 34: BIOS Setup, Hard Disk Drive Sub-Menu Selections97Table 35: BIOS Setup, Removable Drives Sub-menu Selections97Table 36: BIOS Setup, CD/DVD Drives Sub-menu Selections97Table 37: BIOS Setup, Security Menu Options98Table 38: BIOS Setup, Server Menu Selections99Table 39: BIOS Setup, System Management Sub-menu Selections100Table 40: BIOS Setup, Serial Console Features Sub-menu Selections101Table 41: BIOS Setup, Event Log Configuration Sub-menu Selections101Table 42: BIOS Setup, Exit Menu Selections102Table 43: Security Features Operating Model106Table 44: Supported Wake Events111Table 45: Suppoted Management Features by Tier113Table 46: Server Management I2C Bus ID Assignments122Table 47: Power Control Initiators126Table 48: System Reset Sources and Actions127Table 49: SSI Power LED Operation128Table 50: Fault / Status LED129Table 51: Chassis ID LED129Table 52: Suported Channel Assignments134Table 53: LAN Channel Capacity135Table 54: PEF Action Priorities137Table 55: Platform Sensors for On-Board Platform Instrumentation138Table 56. Platform Sensors for Intel Management Modules - Professional and Advanced142Table 57: Memory Error Handling mBMC vs Sahalee153Table 58: Memory Error Handling in non-RAS mode154Table 59: Memory BIOS Messages156Table 60: Boot BIOS Messages157Table 61: Storage Device BIOS Messages157Table 62: Virus Related BIOS Messages160Table 63: System Configuration BIOS Messages160Table 64: CMOS BIOS Messages161Table 65: Miscellaneous BIOS Messages161Table 66: USB BIOS Error Messages161Table 67: SMBIOS BIOS Error Messages162Table 68: Error Codes and Messages162Table 69: Error Codes Sent to the Management Module164Table 70: BIOS Generated Beep Codes165Table 71: Troubleshooting BIOS Beep Codes166Table 72: Boot Block Error Beep Codes166Table 73: BMC Beep Code167Table 74: POST Progress Code LED Example167Table 75: POST Code Checkpoints168Table 76: Bootblock Initialization Code Checkpoints170Table 77: Bootblock Recovery Code Checkpoint171Table 78: DIM Code Checkpoints172Table 79: ACPI Runtime Checkpoints173Table 80: Memory Error Codes173Table 81: Power Connector Pin-out175Table 82: 12V Power Connector (J4J1)175Table 83: Power Supply Signal Connector (J1G1)176Table 84: IDE Power Connector Pinout (U2E1)176Table 85: Low Profile Riser Slot Pinout176Table 86: Full-height Riser Slot Pinout180Table 87: IMM Connector Pinout (J1C1)184Table 88: ICMB Header Pin-out (J1D1)187Table 89: IPMB Connector Pin-out (J3F1)188Table 90: OEM RMC Connector Pinout (J3B2)189Table 91: 100-Pin Flex Cable Connector Pin-out (For Intel Chassis w/Backplane) (J2J1)189Table 92: 50-Pin Control Panel Connector (Intel Chassis w/No Backplane) (J1J2)190Table 93: Control Panel SSI Standard 34-Pin Header Pin-out191Table 94: VGA Connector Pin-out192Table 95: RJ-45 10/100/1000 NIC Connector Pin-out193Table 96: Internal/External 68-pin VHDCI SCSI Connector Pin-out193Table 97: ATA-100 40-pin Connector Pin-out (J3K1)194Table 98: SATA Connector Pin-out (J1H1 and J1H5)195Table 99: Legacy 34-pin Floppy Drive Connector Pin-out (J3K2)196Table 100: External RJ-45 Serial B Port Pin-out196Table 101: Internal 9-pin Serial A Header Pin-out (J1A3)196Table 102: Stacked PS/2 Keyboard and Mouse Port Pin-out197Table 103: External USB Connector Pin-out197Table 104: Internal 1x10 USB Connector Pin-out (J1F1)198Table 105: Internal 2x5 USB Connector (J1G1)198Table 106: CPU1/CPU2 Fan Connector Pin-out (J5F2, J7F1)199Table 107: Intel Server Chassis Fan Header Pin-out (J3K6)199Table 108: 3-Pin Fan Speed Controlled Fan Header (J3K3)200Table 109: Chassis Intrusion Header (J1A1)200Table 110: Hard Drive Activity LED Header(J1A2)200Table 111: Jumper Block Definitions201Table 112: Board Design Specifications202Table 113: P1 Main Power Connector204Table 114: P2 Processor Power Connector204Table 115: P3 Baseboard Signal Connector205Table 116: Peripheral Power Connectors205Table 117: P7 Hard Drive Power Connector205Table 118: Voltage Regulation Limits207Table 119: Transient Load Requirements207Table 120: Capacitve Loading Conditions208Table 121: Ripple and Noise208Table 122: Output Voltage Timing209Table 123: Turn On/Off Timing210Product Certification Markings213Размер: 3,0 МБСтраницы: 225Язык: EnglishПросмотреть