Fiche De DonnéesTable des matièresUniversal Serial Bus Features:1Flexible Oscillator Structure:1Peripheral Highlights:1Extreme Low-Power Management with XLP:1Special Microcontroller Features:1Pin Diagram2Pin Diagram3TABLE 1: PIC18(L)F2X/45K50 Pin Summary5Table of Contents8Most Current Data Sheet9Errata9Customer Notification System91.0 Device Overview111.1 New Core Features111.1.1 XLP Technology111.1.2 Universal Serial Bus (USB)111.1.3 Multiple Oscillator Options and Features111.2 Other Special Features121.3 Details on Individual Family Members12TABLE 1-1: Device Features13FIGURE 1-1: PIC18(L)F2X/45K50 Family Block Diagram14TABLE 1-2: PIC18(L)F2XK50 Pinout I/O Descriptions15TABLE 1-3: PIC18(L)F45K50 Pinout I/O Descriptions192.0 Guidelines for Getting Started with PIC18(L)F2X/45K50 Microcontrollers252.1 Basic Connection Requirements25FIGURE 2-1: Recommended Minimum Connections252.2 Power Supply Pins262.3 Master Clear (MCLR) Pin26FIGURE 2-2: Example of MCLR Pin Connections262.4 Voltage Regulator Pins (Vusb3v3)27FIGURE 2-3: DC Bias Voltage vs. Capacitance Characteristics272.5 ICSP Pins282.6 External Oscillator Pins282.7 Unused I/Os28FIGURE 2-4: Suggested Placement of the Oscillator Circuit293.0 Oscillator Module (With Fail-Safe Clock Monitor)313.1 Overview31FIGURE 3-1: Simplified Oscillator System Block Diagram323.2 Oscillator Control333.2.1 Main System Clock Selection333.2.2 Internal Frequency Selection333.2.3 Low-Frequency Selection333.2.4 Power Management33FIGURE 3-2: Internal Oscillator Mux Block Diagram34TABLE 3-1: PLL_Select Truth Table34FIGURE 3-3: Secondary Oscillator and External Clock Inputs343.3 Register Definitions: Oscillator Control35Register 3-1: OSCCON: Oscillator Control Register35Register 3-2: OSCCON2: Oscillator Control Register 2363.4 Clock Source Modes373.5 External Clock Modes373.5.1 Oscillator Start-up Timer (OST)37TABLE 3-2: Oscillator Delay Examples373.5.2 EC Mode37FIGURE 3-4: External Clock (EC) Mode Operation373.5.3 LP, XT, HS Modes38FIGURE 3-5: Quartz Crystal Operation (LP, XT or HS Mode)38FIGURE 3-6: Ceramic Resonator Operation (XT or HS Mode)383.5.4 External RC Modes39FIGURE 3-7: External RC Modes393.6 Internal Clock Modes393.6.1 INTOSC with I/O or Clockout393.7 Register Definitions: Oscillator Tuning40Register 3-3: OSCTUNE: Oscillator Tuning Register403.7.1 INTRC413.7.2 Frequency Select Bits (IRCF)413.7.3 INTOSC Frequency Drift413.8 PLL Frequency Multiplier423.8.1 PLL in External Oscillator Modes423.8.2 PLL in HFINTOSC Modes423.9 Effects of Power-Managed Modes on the Various Clock Sources423.10 Power-up Delays43TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode433.11 Clock Switching443.11.1 System Clock Select (SCS<1:0>) Bits443.11.2 Oscillator Start-up Time-out Status (OSTS) Bit443.11.3 Clock Switch Timing443.12 Two-Speed Clock Start-up Mode453.12.1 Two-Speed Start-up Mode Configuration453.12.2 Two-Speed Start-up Sequence463.12.3 Checking Two-Speed Clock Status46FIGURE 3-8: Clock Switch Timing463.13 Fail-Safe Clock Monitor47FIGURE 3-9: FSCM Block Diagram473.13.1 Fail-Safe Detection473.13.2 Fail-Safe Operation473.13.3 Fail-Safe Condition Clearing473.13.4 Reset or Wake-up from Sleep47FIGURE 3-10: FSCM Timing Diagram48TABLE 3-4: Registers Associated with Clock Sources48TABLE 3-5: Configuration Registers Associated with Clock Sources483.14 Oscillator Settings for USB493.14.1 Low-Speed Operation49TABLE 3-6: Clock for Low-Speed USB49TABLE 3-7: Oscillator Configuration Options for USB Operation493.15 Active Clock Tuning (ACT) Module503.16 Active Clock Tuning Operation503.17 Active Clock Tuning Source Selection503.18 ACT Lock Status503.19 ACT Out-of-Range Status50FIGURE 3-11: Active Clock Tuning Block Diagram503.20 Active Clock Tuning Update Disable513.21 Interrupts513.22 Operation during Sleep513.23 Register Definitions: Active Clock Tuning Control52Register 3-4: ACTCON: Active Clock Tuning (ACT) Control Register52TABLE 3-8: Summary of Registers Associated with ACT Sources53TABLE 3-9: Summary of Configuration Word with ACT Sources534.0 Power-Managed Modes554.1 Selecting Power-Managed Modes554.1.1 Clock Sources554.1.2 Entering Power-Managed Modes55TABLE 4-1: Power-Managed Modes554.1.3 Multiple Functions of the Sleep Command564.2 Run Modes564.2.1 PRI_RUN Mode564.2.2 SEC_RUN Mode564.2.3 RC_RUN Mode56FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode57FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)57TABLE 4-2: Internal Oscillator Frequency Stability Bits58FIGURE 4-3: Transition Timing From RC_RUN Mode to PRI_RUN Mode584.3 Sleep Mode594.3.1 Voltage Regulator Power Mode59Register 4-1: VREGCON – Voltage Regulator Power Control Register(1)594.4 Idle Modes60FIGURE 4-4: Transition Timing for Entry to Sleep Mode60FIGURE 4-5: Transition Timing for Wake from Sleep (HSPLL)604.4.1 PRI_IDLE Mode604.4.2 SEC_IDLE Mode61FIGURE 4-6: Transition Timing for Entry to Idle Mode61FIGURE 4-7: Transition Timing for Wake from Idle to Run Mode614.4.3 RC_IDLE Mode624.5 Exiting Idle and Sleep Modes624.5.1 Exit by Interrupt624.5.2 Exit by WDT Time-out624.5.3 Exit by Reset634.5.4 Exit without an Oscillator Start-up Delay634.6 Selective Peripheral Module Control634.7 Register Definitions: Peripheral Module Disable64Register 4-2: PMD0: Peripheral Module Disable Register 064Register 4-3: PMD1: Peripheral Module Disable Register 1655.0 Reset675.1 RCON Register67FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit675.2 Register Definitions: Reset Control68Register 5-1: RCON: RESET Control Register685.3 Master Clear (MCLR)695.4 Power-on Reset (POR)69FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)695.5 Brown-out Reset (BOR)705.5.1 Detecting BOR705.5.2 Software Enabled BOR705.5.3 Disabling BOR in Sleep Mode705.5.4 Minimum BOR Enable Time70TABLE 5-1: BOR Configurations715.6 Low-Power BOR (LPBOR)715.7 Device Reset Timers715.7.1 Power-up Timer (PWRT)715.7.2 Oscillator Start-up Timer (OST)715.7.3 PLL Lock Time-out715.7.4 Time-out Sequence71TABLE 5-2: Time-out in Various Situations72FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)72FIGURE 5-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 172FIGURE 5-5: Time-out Sequence on Power-up (Mclr not Tied to Vdd): Case 273FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)73FIGURE 5-7: Time-out Sequence on Por w/PLL Enabled (MCLR Tied to Vdd)745.8 Reset State of Registers75TABLE 5-3: Status Bits, their Significance and the Initialization Condition for RCON Register75TABLE 5-4: Registers Associated with Resets75TABLE 5-5: Configuration Registers Associated with Resets766.0 Memory Organization776.1 Program Memory Organization77FIGURE 6-1: Program Memory Map and Stack for PIC18(L)F2X/45K50 Devices776.1.1 Program Counter786.1.2 Return Address Stack78FIGURE 6-2: Return Address Stack and Associated Registers786.2 Register Definitions: Stack Pointer80Register 6-1: STKPTR: Stack Pointer Register806.2.1 Stack Full and Underflow Resets806.2.2 Fast Register Stack80EXAMPLE 6-1: Fast Register Stack Code Example816.2.3 Look-up Tables in Program Memory81EXAMPLE 6-2: Computed GOTO Using an Offset Value816.3 PIC18 Instruction Cycle826.3.1 Clocking Scheme826.3.2 Instruction Flow/Pipelining82FIGURE 6-3: Clock/ Instruction Cycle82EXAMPLE 6-3: Instruction Pipeline Flow826.3.3 Instructions in Program Memory83FIGURE 6-4: Instructions in Program Memory836.3.4 Two-Word Instructions83EXAMPLE 6-4: Two-Word Instructions836.4 Data Memory Organization846.4.1 USB RAM846.4.2 Bank Select Register (BSR)84FIGURE 6-5: Data Memory Map for PIC18(L)F2X/45K50 Devices85FIGURE 6-6: Use of the Bank Select Register (Direct Addressing)866.4.3 Access Bank876.4.4 General Purpose Register File876.4.5 Special Function Registers87TABLE 6-1: Special Function Register Map for PIC18(L)F2X/45K50 Devices88TABLE 6-2: Register File Summary for PIC18(L)F2X/45K50 Devices896.4.6 Status Register936.5 Register Definitions: Status93Register 6-2: STATUS: STATUS Register936.6 Data Addressing Modes946.6.1 Inherent and Literal Addressing946.6.2 Direct Addressing946.6.3 Indirect Addressing94EXAMPLE 6-5: How to Clear Ram (Bank 1) Using Indirect Addressing94FIGURE 6-7: Indirect Addressing956.7 Data Memory and the Extended Instruction Set966.7.1 Indexed Addressing with Literal Offset966.7.2 Instructions Affected by Indexed Literal Offset Mode96FIGURE 6-8: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)976.7.3 Mapping the Access Bank in Indexed Literal Offset Mode986.8 PIC18 Instruction Execution and the Extended Instruction Set98FIGURE 6-9: Remapping the Access Bank with Indexed Literal Offset Addressing987.0 Flash Program Memory997.1 Table Reads and Table Writes99FIGURE 7-1: Table Read Operation99FIGURE 7-2: Table Write Operation1007.2 Control Registers1007.2.1 EECON1 and EECON2 Registers1007.3 Register Definitions: Memory Control101Register 7-1: EECON1: Data EEPROM Control 1 Register1017.3.1 TABLAT – Table Latch Register1027.3.2 TBLPTR – Table Pointer Register1027.3.3 Table Pointer Boundaries102TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions102FIGURE 7-3: Table Pointer Boundaries Based on Operation1027.4 Reading the Flash Program Memory103FIGURE 7-4: Reads from Flash Program Memory103EXAMPLE 7-1: Reading a Flash Program Memory Word1037.5 Erasing Flash Program Memory1047.5.1 Flash Program Memory Erase Sequence104EXAMPLE 7-2: Erasing a Flash Program Memory Block1047.6 Writing to Flash Program Memory105FIGURE 7-5: Table Writes to Flash Program Memory1057.6.1 Flash Program Memory Write Sequence105EXAMPLE 7-3: Writing to Flash Program Memory106EXAMPLE 7-3: Writing to Flash Program Memory (Continued)1077.6.2 Write Verify1077.6.3 Unexpected Termination of Write Operation1077.6.4 Protection Against Spurious Writes1077.7 Flash Program Operation During Code Protection107TABLE 7-2: Registers Associated with Program Flash Memory1078.0 Data EEPROM Memory1098.1 EEADR Register1098.2 EECON1 and EECON2 Registers109Register 8-1: EECON1: Data EEPROM Control 1 Register1108.3 Reading the Data EEPROM Memory1118.4 Writing to the Data EEPROM Memory1118.5 Write Verify111EXAMPLE 8-1: Data EEPROM Read111EXAMPLE 8-2: Data EEPROM Write1118.6 Operation During Code-Protect1128.7 Protection Against Spurious Write1128.8 Using the Data EEPROM112EXAMPLE 8-3: Data EEPROM Refresh Routine112TABLE 8-1: Registers Associated with Data EEPROM Memory1139.0 8 X 8 Hardware Multiplier1159.1 Introduction1159.2 Operation115EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine115EXAMPLE 9-2: 8 x 8 Signed Multiply Routine115TABLE 9-1: Performance Comparison for Various Multiply Operations115EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm116EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine116EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm116EXAMPLE 9-4: 16 x 16 Signed Multiply Routine11610.0 Interrupts11710.1 Mid-Range Compatibility11710.2 Interrupt Priority11710.3 Interrupt Response117FIGURE 10-1: PIC18 Interrupt Logic11810.4 INTCON Registers11910.5 PIR Registers11910.6 PIE Registers11910.7 IPR Registers11910.8 Register Definitions: Interrupt Control120Register 10-1: INTCON: Interrupt Control Register120Register 10-2: INTCON2: Interrupt Control 2 Register121Register 10-3: INTCON3: Interrupt Control 3 Register122Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1123Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2124Register 10-6: PIR3: Peripheral Interrupt (Flag) Register 3125Register 10-7: PIE1: Peripheral Interrupt Enable (Flag) Register 1126Register 10-8: PIE2: Peripheral Interrupt Enable (Flag) Register 2127Register 10-9: PIE3: Peripheral Interrupt Enable (Flag) Register 3128Register 10-10: IPR1: Peripheral Interrupt Priority Register 1129Register 10-11: IPR2: Peripheral Interrupt Priority Register 2130Register 10-12: IPR3: Peripheral Interrupt Priority Register 313110.9 INTn Pin Interrupts13210.10 TMR0 Interrupt13210.11 PORTB/PORTC Interrupt-on- Change13210.12 Context Saving During Interrupts132EXAMPLE 10-1: Saving Status, WREG and BSR Registers in RAM132TABLE 10-1: Registers Associated with Interrupts133TABLE 10-2: Configuration Registers Associated with Interrupts13311.0 I/O Ports135FIGURE 11-1: Generic I/O Port Operation13511.1 PORTA Registers135EXAMPLE 11-1: Initializing PORTA135TABLE 11-1: PORTA I/O Summary136TABLE 11-2: Registers Associated with PORTA137TABLE 11-3: Configuration Registers Associated with PORTA13711.1.1 PORTA Output Priority138TABLE 11-4: Port Pin Function Priority13911.2 PORTB Registers140EXAMPLE 11-2: Initializing PORTB14011.2.1 PORTB Output Priority14011.3 Additional PORTB Pin Functions14011.3.1 Weak Pull-Ups14011.3.2 Interrupt-On-Change14011.3.3 Alternate Functions141TABLE 11-5: PORTB I/O Summary141TABLE 11-6: Registers Associated with PORTB143TABLE 11-7: Configuration Registers Associated with PORTB14311.4 PORTC Registers144EXAMPLE 11-3: Initializing PORTC14411.4.1 PORTC Output Priority14411.4.2 Interrupt-on-Change144TABLE 11-8: PORTC I/O Summary145TABLE 11-9: Registers Associated with PORTC147TABLE 11-10: Configuration Registers Associated with PORTC14711.5 PORTD Registers148EXAMPLE 11-4: Initializing PORTD14811.5.1 PORTD Output Priority148TABLE 11-11: PORTD I/O Summary149TABLE 11-12: Registers Associated with PORTD15011.6 PORTE Registers15111.6.1 PORTE on 40/44-Pin Devices151EXAMPLE 11-5: Initializing PORTE15111.6.2 PORTE on 28-Pin Devices15111.6.3 RE3 Weak Pull-Up15111.6.4 PORTE Output Priority151TABLE 11-13: PORTE I/O Summary152TABLE 11-14: Registers Associated with PORTE152TABLE 11-15: Configuration Registers Associated with PORTE15211.7 Port Analog Control15311.8 Port Slew Rate Control15311.9 Register Definitions – Port Control153Register 11-1: PORTx(1): PORTx Register153Register 11-2: PORTE: PORTE Register154Register 11-3: ANSELA – PORTA Analog Select Register154Register 11-4: ANSELB – PORTB Analog Select Register155Register 11-5: ANSELC – PORTC Analog Select Register155Register 11-6: ANSELD – PORTD Analog Select Register155Register 11-7: ANSELE – PORTE Analog Select Register156Register 11-8: TRISx: PORTx Tri-State Register(1)156Register 11-9: TRISE: PORTE Tri-State Register156Register 11-10: LATx: Portx Output Latch Register(1)157Register 11-11: LATE: PORTE Output Latch Register(1)157Register 11-12: WPUB: Weak Pull-up PORTB Register157Register 11-13: IOCB: Interrupt-on-Change PORTB Control register158Register 11-14: IOCC: Interrupt-on-Change PORTC Control Register158Register 11-15: SLRCON: Slew Rate Control Register15912.0 Timer0 Module16112.1 Register Definitions: Timer0 Control161Register 12-1: T0CON: Timer0 Control Register16112.2 Timer0 Operation16212.3 Timer0 Reads and Writes in 16-Bit Mode162FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)162FIGURE 12-2: Timer0 Block Diagram (16-Bit Mode)16312.4 Prescaler16312.4.1 Switching Prescaler Assignment16312.5 Timer0 Interrupt163TABLE 12-1: Registers Associated with Timer016313.0 Timer1/3 Module with Gate Control165FIGURE 13-1: Timer1/3 Block Diagram16513.1 Timer1/3 Operation166TABLE 13-1: Timer1/3 Enable Selections16613.2 Clock Source Selection16613.2.1 Internal Clock Source16613.2.2 External Clock Source166TABLE 13-2: Clock Source Selections16613.3 Timer1/3 Prescaler16713.4 Secondary Oscillator16713.5 Timer1/3 Operation in Asynchronous Counter Mode16713.5.1 Reading and Writing Timer1/3 in Asynchronous Counter Mode16713.6 Timer1/3 16-Bit Read/Write Mode167FIGURE 13-2: Timer1/3 16-Bit Read/Write Mode Block Diagram16813.7 Timer1/3 Gate16813.7.1 Timer1/3 Gate Enable168TABLE 13-3: Timer1/3 Gate Enable Selections16813.7.2 Timer1/3 Gate Source Selection168TABLE 13-4: Timer1/3 Gate Sources16813.7.3 Timer1/3 Gate Toggle Mode16913.7.4 Timer1/3 Gate Single-Pulse Mode16913.7.5 Timer1/3 Gate Value Status16913.7.6 Timer1/3 Gate Event Interrupt16913.8 Timer1/3 Interrupt17013.9 Timer1/3 Operation During Sleep17013.10 ECCP/CCP Capture/Compare Time Base17013.11 ECCP/CCP Special Event Trigger170FIGURE 13-3: Timer1/3 Incrementing Edge171FIGURE 13-4: Timer1/3 Gate Enable Mode171FIGURE 13-5: Timer1/3 Gate Toggle Mode172FIGURE 13-6: Timer1/3 Gate Single-Pulse Mode172FIGURE 13-7: Timer1/3 Gate Single-Pulse and Toggle Combined Mode17313.12 Peripheral Module Disable17313.13 Register Definitions: Timer1/3 Control174Register 13-1: TxCON: Timer1/3 Control Register174Register 13-2: TxGCON: Timer1/3 Gate Control Register175TABLE 13-5: Registers Associated with Timer1/3 as a Timer/Counter176TABLE 13-6: Configuration Registers Associated with Timer1/317614.0 Timer2 Module177FIGURE 14-1: Timer2 Block Diagram17714.1 Timer2 Operation17814.2 Timer2 Interrupt17814.3 Timer2 Output17814.4 Timer2 Operation During Sleep17814.5 Peripheral Module Disable17814.6 Register Definitions: Timer2 Control179Register 14-1: T2CON: Timer2 Control Register179TABLE 14-1: Summary of Registers Associated With Timer218015.0 Capture/Compare/PWM Modules18115.1 Capture Mode181FIGURE 15-1: Capture Mode Operation Block Diagram18115.1.1 CCP pin Configuration182TABLE 15-1: CCP Pin Multiplexing18215.1.2 Timer1 Mode Resource18215.1.3 Software Interrupt Mode18215.1.4 CCP Prescaler183EXAMPLE 15-1: Changing Between Capture Prescalers18315.1.5 Capture During Sleep183TABLE 15-2: Registers Associated with Capture184TABLE 15-3: Configuration Registers Associated with Capture18415.2 Compare Mode185FIGURE 15-2: Compare Mode Operation Block Diagram18515.2.1 CCP Pin Configuration18515.2.2 Timerx Mode Resource18515.2.3 Software Interrupt Mode18515.2.4 Special Event Trigger18615.2.5 Compare During Sleep186TABLE 15-4: Registers Associated with Compare187TABLE 15-5: Configuration Registers Associated with Capture18715.3 PWM Overview18815.3.1 Standard PWM Operation188FIGURE 15-3: CCP PWM Output Signal188FIGURE 15-4: Simplified PWM Block Diagram18815.3.2 Setup for PWM Operation18815.3.3 PWM Period189EQUATION 15-1: PWM Period18915.3.4 PWM Duty Cycle189EQUATION 15-2: Pulse Width189EQUATION 15-3: Duty Cycle Ratio18915.3.5 PWM Resolution190EQUATION 15-4: PWM Resolution190TABLE 15-6: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)190TABLE 15-7: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)190TABLE 15-8: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)19015.3.6 Operation in Sleep Mode19015.3.7 Changes in System Clock Frequency19015.3.8 Effects of Reset190TABLE 15-9: Registers Associated with Standard PWM191TABLE 15-10: Configuration Registers Associated with Capture19115.4 PWM (Enhanced Mode)192FIGURE 15-5: Example Simplified Block Diagram of the Enhanced PWM Mode192TABLE 15-11: Example Pin Assignments for Various PWM Enhanced Modes193FIGURE 15-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)193FIGURE 15-7: Example Enhanced PWM Output Relationships (Active-Low State)19415.4.1 Half-Bridge Mode195FIGURE 15-8: Example of Half- Bridge PWM Output195FIGURE 15-9: Example of Half-Bridge Applications19515.4.2 Full-Bridge Mode196FIGURE 15-10: Example of Full-Bridge Application196FIGURE 15-11: Example of Full-Bridge PWM Output197FIGURE 15-12: Example of PWM Direction Change198FIGURE 15-13: Example of PWM Direction Change at Near 100% Duty Cycle19915.4.3 Enhanced PWM Auto- shutdown Mode199FIGURE 15-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)20015.4.4 Auto-Restart Mode200FIGURE 15-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)20015.4.5 Programmable Dead-Band Delay Mode201FIGURE 15-16: Example of Half- Bridge PWM Output201FIGURE 15-17: Example of Half-Bridge Applications20115.4.6 PWM Steering Mode202FIGURE 15-18: Simplified Steering Block Diagram20215.4.7 Start-up Considerations203FIGURE 15-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)203FIGURE 15-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)20315.4.8 Setup for ECCP PWM Operation using ECCP1 and Timer2204TABLE 15-12: Registers Associated with Enhanced PWM20515.5 Register Definitions: ECCP Control206Register 15-1: CCPXCON: Standard CCPx Control Register206Register 15-2: CCPxCON: Enhanced CCPx Control Register207Register 15-3: CCPTMRS: PWM Timer Selection Control Register 0209Register 15-4: ECCPxAS: CCPx Auto-Shutdown Control Register210Register 15-5: PWMxCON: Enhanced PWM Control Register211Register 15-6: PSTRxCON: PWM Steering Control Register(1)21116.0 Master Synchronous Serial Port (MSSP) Module21316.1 Module Overview213FIGURE 16-1: MSSP Block Diagram (SPI mode)213FIGURE 16-2: MSSP Block Diagram (I2C™ Master mode)214FIGURE 16-3: MSSP Block Diagram (I2C™ Slave mode)21516.2 SPI Mode Overview216FIGURE 16-4: SPI Master and Multiple Slave Connection21716.2.1 SPI Mode Registers21716.2.2 SPI Mode Operation217FIGURE 16-5: SPI Master/Slave Connection21816.2.3 SPI Master Mode219FIGURE 16-6: SPI Mode Waveform (Master Mode)21916.2.4 SPI Slave Mode22016.2.5 Slave Select Synchronization220FIGURE 16-7: SPI Daisy-Chain Connection221FIGURE 16-8: Slave Select Synchronous Waveform221FIGURE 16-9: SPI Mode Waveform (Slave Mode With CKE = 0)222FIGURE 16-10: SPI Mode Waveform (SLAve Mode With CKE = 1)22216.2.6 SPI Operation IN Sleep Mode223TABLE 16-1: Registers Associated with SPI Operation22316.3 I2C Mode Overview224FIGURE 16-11: I2C™ Master/ Slave Connection22416.3.1 Clock Stretching22516.3.2 Arbitration22516.4 I2C Mode Operation22616.4.1 Byte Format22616.4.2 Definition of I2C Terminology22616.4.3 SDA and SCL Pins22616.4.4 SDA Hold Time226TABLE 16-2: I2C™ Bus Terms22616.4.5 Start Condition22716.4.6 STOP Condition22716.4.7 Restart Condition22716.4.8 START/STOP Condition Interrupt Masking227FIGURE 16-12: I2C™ START and STOP Conditions227FIGURE 16-13: I2C™ Restart Condition22716.4.9 Acknowledge Sequence22816.5 I2C Slave Mode Operation22816.5.1 Slave Mode Addresses22816.5.2 Slave Reception229FIGURE 16-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)230FIGURE 16-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)231FIGURE 16-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)232FIGURE 16-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)23316.5.3 SLAVE Transmission234FIGURE 16-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)235FIGURE 16-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)23716.5.4 Slave Mode 10-bit Address Reception23816.5.5 10-bit Addressing With Address Or Data Hold238FIGURE 16-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)239FIGURE 16-21: I2C Slave, 10-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0)240FIGURE 16-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)24116.5.6 Clock Stretching24216.5.7 Clock Synchronization and the CKP bit242FIGURE 16-23: Clock Synchronization Timing24216.5.8 General Call Address Support243FIGURE 16-24: Slave Mode General Call Address Sequence24316.5.9 SSPx Mask Register24316.6 I2C Master Mode24416.6.1 I2C Master Mode Operation24416.6.2 Clock Arbitration245FIGURE 16-25: Baud Rate Generator Timing with Clock Arbitration24516.6.3 WCOL Status Flag24516.6.4 I2C Master Mode Start Condition Timing246FIGURE 16-26: First Start Bit Timing24616.6.5 I2C Master Mode Repeated Start Condition Timing247FIGURE 16-27: Repeat Start Condition Waveform24716.6.6 I2C Master Mode Transmission248FIGURE 16-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)24916.6.7 I2C Master Mode Reception250FIGURE 16-29: I2C™ Master Mode Waveform (Reception, 7-Bit Address)25116.6.8 Acknowledge Sequence Timing25216.6.9 Stop Condition Timing252FIGURE 16-30: Acknowledge Sequence Waveform252FIGURE 16-31: Stop Condition Receive or Transmit Mode25216.6.10 Sleep Operation25316.6.11 Effects of a Reset25316.6.12 Multi-Master Mode25316.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration254FIGURE 16-32: Bus Collision Timing for Transmit and Acknowledge254FIGURE 16-33: Bus Collision During Start Condition (SDA Only)255FIGURE 16-34: Bus Collision During Start Condition (SCL = 0)256FIGURE 16-35: BRG Reset Due to Sda Arbitration During Start Condition256FIGURE 16-36: Bus Collision During a Repeated Start Condition (Case 1)257FIGURE 16-37: Bus Collision During Repeated Start Condition (Case 2)257FIGURE 16-38: Bus Collision During a Stop Condition (Case 1)258FIGURE 16-39: Bus Collision During a Stop Condition (Case 2)258TABLE 16-3: Registers Associated with I2C™ Operation25916.7 Baud Rate Generator260FIGURE 16-40: Baud Rate Generator Block Diagram260TABLE 16-4: MSSP Clock Rate w/BRG26016.8 Register Definitions: MSSP Control261Register 16-1: SSPxSTAT: SSPx STATUS Register261Register 16-2: SSPxCON1: SSPx Control Register 1262Register 16-3: SSPxCON2: SSPx Control Register 2264Register 16-4: SSPxCON3: SSPx Control Register 3265Register 16-5: SSPxMSK: SSPx Mask Register266Register 16-6: SSPxADD: MSSP Address and Baud Rate Register (I2C Mode)26717.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)269FIGURE 17-1: EUSART Transmit Block Diagram269FIGURE 17-2: EUSART Receive Block Diagram27017.1 EUSART Asynchronous Mode27117.1.1 EUSART Asynchronous Transmitter271FIGURE 17-3: Asynchronous Transmission272FIGURE 17-4: Asynchronous Transmission (Back-to-Back)273TABLE 17-1: Registers Associated with Asynchronous Transmission27317.1.2 EUSART Asynchronous Receiver274FIGURE 17-5: Asynchronous Reception277TABLE 17-2: Registers Associated with Asynchronous Reception27717.2 Clock Accuracy with Asynchronous Operation27817.3 Register Definitions: EUSART Control279Register 17-1: TXSTAx: Transmit Status and Control Register279Register 17-2: RCSTAx: Receive Status and Control Register280Register 17-3: BAUDCONx: Baud Rate Control Register28117.4 EUSART Baud Rate Generator (BRG)282EXAMPLE 17-1: Calculating Baud Rate Error282TABLE 17-3: Baud Rate Formulas282TABLE 17-4: Registers Associated with Baud Rate Generator283TABLE 17-5: BAUD Rates for Asynchronous Modes28317.4.1 Auto-Baud Detect286TABLE 17-6: BRG Counter Clock Rates286FIGURE 17-6: Automatic Baud Rate Calibration28617.4.2 Auto-baud Overflow28717.4.3 Auto-Wake-up on Break287FIGURE 17-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation288FIGURE 17-8: Auto-Wake-up Bit (WUE) Timings During Sleep28817.4.4 BREAK Character Sequence28917.4.5 Receiving a BREAK Character289FIGURE 17-9: Send Break Character Sequence28917.5 EUSART Synchronous Mode29017.5.1 Synchronous Master Mode290FIGURE 17-10: Synchronous Transmission291FIGURE 17-11: Synchronous Transmission (Through TXEN)291TABLE 17-7: Registers Associated with Synchronous Master Transmission292FIGURE 17-12: Synchronous Reception (Master Mode, SREN)294TABLE 17-8: Registers Associated with Synchronous Master Reception29417.5.2 Synchronous Slave Mode295TABLE 17-9: Registers Associated with Synchronous Slave Transmission296TABLE 17-10: Registers Associated with Synchronous Slave Reception29718.0 Analog-to-Digital Converter (ADC) Module299FIGURE 18-1: ADC Block Diagram29918.1 ADC Configuration30018.1.1 Port Configuration30018.1.2 Channel Selection30018.1.3 ADC Voltage Reference30018.1.4 Selecting and Configuring Acquisition Time30018.1.5 Conversion Clock30118.1.6 Interrupts301TABLE 18-1: ADC Clock Period (Tad) vs. Device Operating Frequencies30118.1.7 Result Formatting302FIGURE 18-2: 10-Bit A/D Conversion Result Format30218.2 ADC Operation30318.2.1 Starting a Conversion303FIGURE 18-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, TACQ = 0)303FIGURE 18-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, TACQ = 4 TAD)30318.2.2 Completion of a Conversion30418.2.3 Discharge30418.2.4 Terminating a Conversion30418.2.5 Delay Between Conversions30418.2.6 ADC Operation in Power- Managed Modes30418.2.7 ADC Operation During Sleep30418.2.8 Special Event Trigger30418.2.9 Peripheral Module Disable30418.2.10 A/D Conversion Procedure305EXAMPLE 18-1: A/D Conversion30518.3 Register Definitions: ADC Control306Register 18-1: ADCON0: A/D Control Register 0306Register 18-2: ADCON1: A/D Control Register 1307Register 18-3: ADCON2: A/D Control Register 2308Register 18-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0309Register 18-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0309Register 18-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1309Register 18-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 130918.4 A/D Acquisition Requirements310EQUATION 18-1: Acquisition Time Example310FIGURE 18-5: Analog Input Model311FIGURE 18-6: ADC Transfer Function311TABLE 18-2: Registers Associated with A/D Operation312TABLE 18-3: Configuration Registers Associated with the ADC Module31219.0 Comparator Module31319.1 Comparator Overview313FIGURE 19-1: Single Comparator313FIGURE 19-2: Comparator C1/C2 Simplified Block Diagram31419.2 Comparator Control31519.2.1 Comparator Enable31519.2.2 Comparator Input Selection31519.2.3 Comparator Reference Selection31519.2.4 Comparator Output Selection31519.2.5 Comparator Output Polarity315TABLE 19-1: Comparator Output State vs. Input Conditions31519.2.6 Comparator Speed Selection31519.3 Comparator Response Time31519.4 Comparator Interrupt Operation31619.4.1 Presetting the Mismatch Latches316FIGURE 19-3: Comparator Interrupt Timing W/O CMxCON0 Read316FIGURE 19-4: Comparator Interrupt Timing With CMxCON0 Read31619.5 Operation During Sleep31719.6 Effects of a Reset31719.7 Analog Input Connection Considerations317FIGURE 19-5: Analog Input Model31719.8 Additional Comparator Features31819.8.1 Simultaneous Comparator Output Read31819.8.2 Internal Reference Selection31819.8.3 Synchronizing Comparator Output to Timer131819.9 Register Definitions: Comparator Control319Register 19-1: CMxCON0: Comparator x Control Register319Register 19-2: CM2CON1: Comparator 1 and 2 Control Register320TABLE 19-2: Registers Associated with Comparator Module32120.0 Charge Time Measurement Unit (CTMU)323FIGURE 20-1: CTMU Block Diagram32320.1 CTMU Operation32420.1.1 Theory of Operation32420.1.2 Current Source32420.1.3 Edge Selection and Control32420.1.4 Edge Status32520.1.5 Interrupts32520.2 CTMU Module Initialization32520.3 Calibrating the CTMU Module32620.3.1 Current Source Calibration326FIGURE 20-2: CTMU Current Source Calibration Circuit326EXAMPLE 20-1: Setup for CTMU Calibration Routines327EXAMPLE 20-2: Current Calibration Routine32820.3.2 Capacitance Calibration329EXAMPLE 20-3: Capacitance Calibration Routine33020.4 Measuring Capacitance with the CTMU33120.4.1 Absolute Capacitance Measurement33120.4.2 Relative Charge Measurement331EXAMPLE 20-4: Routine for Capacitive Touch Switch33220.5 Measuring Time with the CTMU Module333FIGURE 20-3: Typical Connections and Internal Configuration for Time Measurement33320.6 Creating a Delay with the CTMU Module334FIGURE 20-4: Typical Connections and Internal Configuration for Pulse Delay Generation33420.7 Operation During Sleep/Idle Modes33420.7.1 Sleep Mode33420.7.2 Idle Mode33420.8 CTMU Peripheral Module Disable (PMD)33420.9 Effects of a Reset on CTMU33520.10 Registers33520.11 Register Definitions: CTMU Control335Register 20-1: CTMUCONH: CTMU Control Register 0335Register 20-2: CTMUCONL: CTMU Control Register 1336Register 20-3: CTMUICON: CTMU Current Control Register337TABLE 20-1: Registers Associated with CTMU Module33721.0 SR Latch33921.1 Latch Operation33921.2 Latch Output33921.3 DIVSRCLK Clock Generation33921.4 Effects of a Reset339FIGURE 21-1: DIVSRCLK Block Diagram340FIGURE 21-2: SR Latch Simplified Block Diagram340TABLE 21-1: DIVSRCLK Frequency Table34121.5 Register Definitions: SR Latch Control342Register 21-1: SRCON0: SR Latch Control Register342Register 21-2: SRCON1: SR Latch Control Register 1343TABLE 21-2: Registers Associated with the SR Latch34322.0 Fixed Voltage Reference (FVR)34522.1 Independent Gain Amplifiers34522.2 FVR Stabilization Period345FIGURE 22-1: Voltage Reference Block Diagram34522.3 Register Definitions: FVR Control346Register 22-1: VREFCON0: Fixed Voltage Reference Control Register346TABLE 22-1: Summary of Registers Associated with Fixed Voltage Reference34623.0 Digital-to-Analog Converter (DAC) Module34723.1 Output Voltage Selection347EQUATION 23-1: DAC Output Voltage34723.2 Ratiometric Output Level34723.3 Low-Power Voltage State34723.4 Output Clamped to Positive Voltage Source34723.5 Output Clamped to Negative Voltage Source34723.6 DAC Voltage Reference Output347FIGURE 23-1: Digital-to-Analog Converter Block Diagram348FIGURE 23-2: Voltage Reference Output Buffer Example34823.7 Operation During Sleep34923.8 Effects of a Reset34923.9 Register Definitions: DAC Control349Register 23-1: VREFCON1: Voltage Reference Control Register 0349Register 23-2: VREFCON2: Voltage Reference Control Register 1350TABLE 23-1: Registers Associated with DAC Module35024.0 Universal Serial Bus (USB)35124.1 Overview of the USB Peripheral351FIGURE 24-1: USB Peripheral and Options35124.2 USB Status and Control35224.2.1 USB Control Register (UCON)352Register 24-1: UCON: USB Control Register35324.2.2 USB Configuration Register (UCFG)354Register 24-2: UCFG: USB Configuration Register (Banked F39h)355FIGURE 24-2: External Circuitry35624.2.3 USB Status Register (USTAT)357FIGURE 24-3: USTAT FIFO357Register 24-3: USTAT: USB Status Register (Access F64h)35724.2.4 USB Endpoint Control358Register 24-4: UEPn: USB Endpoint n Control Register (UEP0 Through UEP15)35824.2.5 USB Address Register (UADDR)35924.2.6 USB Frame Number Registers (UFRMH:UFRML)35924.3 USB RAM359FIGURE 24-4: Implementation of USB RAM in Data Memory Space35924.4 Buffer Descriptors and the Buffer Descriptor Table36024.4.1 BD Status and Configuration360FIGURE 24-5: Example of a Buffer Descriptor360TABLE 24-1: Effect of DTSEN Bit on Odd/Even (DATA0/DATA1) Packet Reception361Register 24-5: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), CPU Mode (Banked 4xxh)36224.4.2 BD Byte Count36324.4.3 BD Address Validation363Register 24-6: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), SIE Mode (Data Returned By the Side to the MCU)36324.4.4 Ping-Pong Buffering364FIGURE 24-6: Buffer Descriptor Table Mapping for Buffering Modes364TABLE 24-2: Assignment of Buffer Descriptors for the Different Buffering Modes365TABLE 24-3: Summary of USB Buffer Descriptor Table Registers36524.5 USB Interrupts366FIGURE 24-7: USB Interrupt Logic Funnel366FIGURE 24-8: Example of a USB Transaction and Interrupt Events36624.5.1 USB Interrupt Status Register (UIR)367Register 24-7: UIR: USB Interrupt Status Register367EXAMPLE 24-1: Clearing ACTVIF Bit (UIR<2>)36824.5.2 USB Interrupt Enable Register (UIE)369Register 24-8: UIE: USB Interrupt Enable Register36924.5.3 USB Error Interrupt Status Register (UEIR)370Register 24-9: UEIR: USB Error Interrupt Status Register37024.5.4 USB Error Interrupt Enable Register (UEIE)371Register 24-10: UEIE: USB Error Interrupt Enable Register37124.6 USB Power Modes37224.6.1 Bus Power Only372FIGURE 24-9: Bus Power Only37224.6.2 Self-Power Only372FIGURE 24-10: Self-Power Only37224.6.3 Dual Power with Self-Power Dominance373FIGURE 24-11: Dual Power Example37324.6.4 USB Transceiver Current Consumption373EQUATION 24-1: Estimating USB Transceiver Current Consumption374EXAMPLE 24-2: Calculating USB Transceiver Current†37424.7 Oscillator37524.8 Interrupt-On-Change for D+/D- pins37524.9 USB Firmware and Drivers375TABLE 24-4: Registers Associated with USB Module Operation(1)37624.10 Overview of USB37724.10.1 Layered Framework37724.10.2 Frames37724.10.3 Transfers37724.10.4 Power377FIGURE 24-12: USB Layers37724.10.5 Enumeration37824.10.6 Descriptors37824.10.7 Bus Speed37824.10.8 Class Specifications and Drivers37825.0 High/Low-Voltage Detect (HLVD)37925.1 Register – HLVD Control379Register 25-1: HLVDCON: High/Low-Voltage Detect Control Register37925.2 Operation380FIGURE 25-1: HLVD Module Block Diagram (with External Input)38025.3 HLVD Setup38125.4 Current Consumption38125.5 HLVD Start-up Time381FIGURE 25-2: Low-Voltage Detect Operation (VDIRMAG = 0)381FIGURE 25-3: High-Voltage Detect Operation (VDIRMAG = 1)38225.6 Applications382FIGURE 25-4: Typical Low-Voltage Detect Application38225.7 Operation During Sleep38325.8 Effects of a Reset383TABLE 25-1: Registers Associated with High/Low-Voltage Detect Module38326.0 Special Features of the CPU38526.1 Configuration Bits385TABLE 26-1: Configuration Bits and Device IDs38626.2 Register Definitions: Configuration Word387Register 26-1: CONFIG1L: Configuration Register 1 Low387Register 26-2: CONFIG1H: Configuration Register 1 High388Register 26-3: CONFIG2L: Configuration Register 2 Low389Register 26-4: CONFIG2H: Configuration Register 2 High390Register 26-5: CONFIG3H: Configuration Register 3 High391Register 26-6: CONFIG4L: Configuration Register 4 Low392Register 26-7: CONFIG5L: Configuration Register 5 Low393Register 26-8: CONFIG5H: Configuration Register 5 High393Register 26-9: CONFIG6L: Configuration Register 6 Low394Register 26-10: CONFIG6H: Configuration Register 6 High395Register 26-11: CONFIG7L: Configuration Register 7 Low395Register 26-12: CONFIG7H: Configuration Register 7 High396Register 26-13: DEVID1: Device ID Register 1396Register 26-14: DEVID2: Device ID Register 2396TABLE 26-2: Device ID Table for the PIC18(L)F2X/45K50 Family39726.3 Watchdog Timer (WDT)398FIGURE 26-1: WDT Block Diagram39826.3.1 Control Register39926.4 Register Definitions: WDT Control399Register 26-15: WDTCON: Watchdog Timer Control Register399TABLE 26-3: Registers Associated with Watchdog Timer399TABLE 26-4: Configuration Registers Associated with Watchdog Timer39926.5 Program Verification and Code Protection400FIGURE 26-2: Code-Protected Program Memory for PIC18(L)F2X/45K50400TABLE 26-5: Configuration Registers Associated with Code Protection40026.5.1 Program Memory Code Protection401FIGURE 26-3: Table Write (WRTn) Disallowed401FIGURE 26-4: External Block Table Read (EBTRn) Disallowed402FIGURE 26-5: Internal Block Table Read (EBTRn) Allowed40226.5.2 Data EEPROM Code Protection40326.5.3 Configuration Register Protection40326.6 ID Locations40326.7 In-Circuit Serial Programming40326.8 In-Circuit Debugger403TABLE 26-6: Debugger Resources40326.9 Special ICPORT Features (44-Pin TQFP Package Only)40326.9.1 Dedicated ICD/ICSP Port403TABLE 26-7: Equivalent Pins for Legacy and Dedicated ICD/ICSP™ Ports40326.10 Single-Supply ICSP Programming40427.0 Instruction Set Summary40527.1 Standard Instruction Set405TABLE 27-1: Opcode Field Descriptions406FIGURE 27-1: General Format for Instructions407TABLE 27-2: PIC18 Instruction Set40827.1.1 Standard Instruction Set41127.2 Extended Instruction Set44727.2.1 Extended Instruction Syntax447TABLE 27-3: Extensions to the PIC18 Instruction Set44727.2.2 Extended Instruction Set44827.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode45227.2.4 Considerations when Enabling the Extended Instruction Set45227.2.5 Special Considerations with Microchip MPLAB® IDE Tools45428.0 Development Support45529.0 Electrical Characteristics459Absolute Maximum Ratings (†)459FIGURE 29-1: PIC18LF2X/45K50 Family Voltage-Frequency Graph (Industrial Temperature)460FIGURE 29-2: PIC18F2X/45K50 Family Voltage-Frequency Graph (Industrial Temperature)46029.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/45K5046129.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/45K5046229.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/45K5046429.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/45K5046629.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/45K5046829.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/45K5046929.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/45K5047029.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/45K5047229.9 Memory Programming Requirements47429.10 USB Module Specifications47529.11 Analog Characteristics476TABLE 29-1: Comparator Specifications476TABLE 29-2: DIGITAL-TO-ANALOG CONVERTER (DAC) Specifications476TABLE 29-3: Fixed Voltage Reference (FVR) Specifications477TABLE 29-4: Charge Time Measurement Unit (CTMU) Specifications477FIGURE 29-3: High/Low-Voltage Detect Characteristics477TABLE 29-5: High/Low-Voltage Detect Characteristics47829.12 AC (Timing) Characteristics47929.12.1 Timing Parameter Symbology47929.12.2 Timing Conditions480TABLE 29-6: Temperature and Voltage Specifications – AC480FIGURE 29-4: Load Conditions for Device Timing Specifications48029.12.3 Timing Diagrams and Specifications481FIGURE 29-5: External Clock Timing (All Modes Except PLL)481TABLE 29-7: External Clock Timing Requirements481TABLE 29-8: PLL Clock Timing Specifications482TABLE 29-9: AC Characteristics: Internal Oscillators Accuracy (PIC18(L)F2X/45K50)482FIGURE 29-6: CLKO and I/O Timing483TABLE 29-10: CLKO and I/O Timing Requirements483FIGURE 29-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing484FIGURE 29-8: Brown-out Reset Timing484TABLE 29-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements485FIGURE 29-9: Timer0 and Timer1 External Clock Timings485TABLE 29-12: Timer0 and Timer1/3 External Clock Requirements486FIGURE 29-10: Capture/Compare/PWM Timings (All CCP Modules)486TABLE 29-13: Capture/Compare/PWM Requirements (All CCP Modules)487FIGURE 29-11: Example SPI Master Mode Timing (CKE = 0)487TABLE 29-14: Example SPI Mode Requirements (Master Mode, CKE = 0 or 1)488FIGURE 29-12: Example SPI Master Mode Timing (CKE = 1)488FIGURE 29-13: Example SPI Slave Mode Timing (CKE = 0)489TABLE 29-15: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0 or 1)489FIGURE 29-14: Example SPI Slave Mode Timing (CKE = 1)490FIGURE 29-15: I2C™ Bus Start/Stop Bits Timing490TABLE 29-16: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)491FIGURE 29-16: I2C™ Bus Data Timing491TABLE 29-17: I2C™ Bus Data Requirements (Slave Mode)492FIGURE 29-17: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms493TABLE 29-18: Master SSP I2C™ Bus Start/Stop Bits Requirements493FIGURE 29-18: Master SSP I2C™ Bus Data Timing493TABLE 29-19: Master SSP I2C™ Bus Data Requirements494FIGURE 29-19: EUSART Synchronous Transmission (Master/Slave) Timing495TABLE 29-20: EUSART Synchronous Transmission Requirements495FIGURE 29-20: EUSART Synchronous Receive (Master/Slave) Timing495TABLE 29-21: EUSART Synchronous Receive Requirements495TABLE 29-22: A/D Converter Characteristics: PIC18(L)F2X/45K50496FIGURE 29-21: A/D Conversion Timing496TABLE 29-23: A/D Conversion Requirements (PIC18(L)F2X/45K50)49730.0 DC and AC Characteristics Graphs and Charts49931.0 Packaging Information50131.1 Package Marking Information50131.2 Package Details504Appendix A: Revision History519Revision A (August 2012)519Appendix B: Device Differences520TABLE B-1: Device Differences520INDEX521A521B521C522D523E523F524G524H524I524L525M525N525O525P526R526S527T527U529V529W529X529Notes:530The Microchip Web Site531Customer Change Notification Service531Customer Support531Reader Response532Product Identification System533Corporate Office536Atlanta536Boston536Chicago536Cleveland536Fax: 216-447-0643536Dallas536Detroit536Indianapolis536Toronto536Fax: 852-2401-3431536Australia - Sydney536China - Beijing536China - Shanghai536India - Bangalore536Korea - Daegu536Korea - Seoul536Singapore536Taiwan - Taipei536Fax: 43-7242-2244-393536Denmark - Copenhagen536France - Paris536Germany - Munich536Italy - Milan536Spain - Madrid536UK - Wokingham536Worldwide Sales and Service536Taille: 8,7 MoPages: 536Language: EnglishOuvrir le manuel