用户手册 — Microchip Technology DM163025-1

目录

• Universal Serial Bus Features:

  1
• Flexible Oscillator Structure:

  1
• Peripheral Highlights:

  1
• Extreme Low-Power Management with XLP:

  1
• Special Microcontroller Features:

  1
• Pin Diagram

  2
• Pin Diagram

  3
• TABLE 1: PIC18(L)F2X/45K50 Pin Summary

  5
  • Table of Contents

    8
  • Most Current Data Sheet

    9
  • Errata

    9
  • Customer Notification System

    9
• 1.0 Device Overview

  11
  • 1.1 New Core Features

    11
    • 1.1.1 XLP Technology

      11
    • 1.1.2 Universal Serial Bus (USB)

      11
    • 1.1.3 Multiple Oscillator Options and Features

      11
  • 1.2 Other Special Features

    12
  • 1.3 Details on Individual Family Members

    12
    • TABLE 1-1: Device Features

      13
    • FIGURE 1-1: PIC18(L)F2X/45K50 Family Block Diagram

      14
    • TABLE 1-2: PIC18(L)F2XK50 Pinout I/O Descriptions

      15
    • TABLE 1-3: PIC18(L)F45K50 Pinout I/O Descriptions

      19
• 2.0 Guidelines for Getting Started with PIC18(L)F2X/45K50 Microcontrollers

  25
  • 2.1 Basic Connection Requirements

    25
    • FIGURE 2-1: Recommended Minimum Connections

      25
  • 2.2 Power Supply Pins

    26
  • 2.3 Master Clear (MCLR) Pin

    26
    • FIGURE 2-2: Example of MCLR Pin Connections

      26
  • 2.4 Voltage Regulator Pins (Vusb3v3)

    27
    • FIGURE 2-3: DC Bias Voltage vs. Capacitance Characteristics

      27
  • 2.5 ICSP Pins

    28
  • 2.6 External Oscillator Pins

    28
  • 2.7 Unused I/Os

    28
    • FIGURE 2-4: Suggested Placement of the Oscillator Circuit

      29
• 3.0 Oscillator Module (With Fail-Safe Clock Monitor)

  31
  • 3.1 Overview

    31
    • FIGURE 3-1: Simplified Oscillator System Block Diagram

      32
  • 3.2 Oscillator Control

    33
    • 3.2.1 Main System Clock Selection

      33
    • 3.2.2 Internal Frequency Selection

      33
    • 3.2.3 Low-Frequency Selection

      33
    • 3.2.4 Power Management

      33
      • FIGURE 3-2: Internal Oscillator Mux Block Diagram

        34
      • TABLE 3-1: PLL_Select Truth Table

        34
      • FIGURE 3-3: Secondary Oscillator and External Clock Inputs

        34
  • 3.3 Register Definitions: Oscillator Control

    35
    • Register 3-1: OSCCON: Oscillator Control Register

      35
    • Register 3-2: OSCCON2: Oscillator Control Register 2

      36
  • 3.4 Clock Source Modes

    37
  • 3.5 External Clock Modes

    37
    • 3.5.1 Oscillator Start-up Timer (OST)

      37
      • TABLE 3-2: Oscillator Delay Examples

        37
    • 3.5.2 EC Mode

      37
      • FIGURE 3-4: External Clock (EC) Mode Operation

        37
    • 3.5.3 LP, XT, HS Modes

      38
      • FIGURE 3-5: Quartz Crystal Operation (LP, XT or HS Mode)

        38
      • FIGURE 3-6: Ceramic Resonator Operation (XT or HS Mode)

        38
    • 3.5.4 External RC Modes

      39
      • FIGURE 3-7: External RC Modes

        39
  • 3.6 Internal Clock Modes

    39
    • 3.6.1 INTOSC with I/O or Clockout

      39
  • 3.7 Register Definitions: Oscillator Tuning

    40
    • Register 3-3: OSCTUNE: Oscillator Tuning Register

      40
    • 3.7.1 INTRC

      41
    • 3.7.2 Frequency Select Bits (IRCF)

      41
    • 3.7.3 INTOSC Frequency Drift

      41
  • 3.8 PLL Frequency Multiplier

    42
    • 3.8.1 PLL in External Oscillator Modes

      42
    • 3.8.2 PLL in HFINTOSC Modes

      42
  • 3.9 Effects of Power-Managed Modes on the Various Clock Sources

    42
  • 3.10 Power-up Delays

    43
    • TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode

      43
  • 3.11 Clock Switching

    44
    • 3.11.1 System Clock Select (SCS<1:0>) Bits

      44
    • 3.11.2 Oscillator Start-up Time-out Status (OSTS) Bit

      44
    • 3.11.3 Clock Switch Timing

      44
  • 3.12 Two-Speed Clock Start-up Mode

    45
    • 3.12.1 Two-Speed Start-up Mode Configuration

      45
    • 3.12.2 Two-Speed Start-up Sequence

      46
    • 3.12.3 Checking Two-Speed Clock Status

      46
      • FIGURE 3-8: Clock Switch Timing

        46
  • 3.13 Fail-Safe Clock Monitor

    47
    • FIGURE 3-9: FSCM Block Diagram

      47
    • 3.13.1 Fail-Safe Detection

      47
    • 3.13.2 Fail-Safe Operation

      47
    • 3.13.3 Fail-Safe Condition Clearing

      47
    • 3.13.4 Reset or Wake-up from Sleep

      47
      • FIGURE 3-10: FSCM Timing Diagram

        48
      • TABLE 3-4: Registers Associated with Clock Sources

        48
      • TABLE 3-5: Configuration Registers Associated with Clock Sources

        48
  • 3.14 Oscillator Settings for USB

    49
    • 3.14.1 Low-Speed Operation

      49
      • TABLE 3-6: Clock for Low-Speed USB

        49
      • TABLE 3-7: Oscillator Configuration Options for USB Operation

        49
  • 3.15 Active Clock Tuning (ACT) Module

    50
  • 3.16 Active Clock Tuning Operation

    50
  • 3.17 Active Clock Tuning Source Selection

    50
  • 3.18 ACT Lock Status

    50
  • 3.19 ACT Out-of-Range Status

    50
    • FIGURE 3-11: Active Clock Tuning Block Diagram

      50
  • 3.20 Active Clock Tuning Update Disable

    51
  • 3.21 Interrupts

    51
  • 3.22 Operation during Sleep

    51
  • 3.23 Register Definitions: Active Clock Tuning Control

    52
    • Register 3-4: ACTCON: Active Clock Tuning (ACT) Control Register

      52
    • TABLE 3-8: Summary of Registers Associated with ACT Sources

      53
    • TABLE 3-9: Summary of Configuration Word with ACT Sources

      53
• 4.0 Power-Managed Modes

  55
  • 4.1 Selecting Power-Managed Modes

    55
    • 4.1.1 Clock Sources

      55
    • 4.1.2 Entering Power-Managed Modes

      55
      • TABLE 4-1: Power-Managed Modes

        55
    • 4.1.3 Multiple Functions of the Sleep Command

      56
  • 4.2 Run Modes

    56
    • 4.2.1 PRI_RUN Mode

      56
    • 4.2.2 SEC_RUN Mode

      56
    • 4.2.3 RC_RUN Mode

      56
      • FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode

        57
      • FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)

        57
      • TABLE 4-2: Internal Oscillator Frequency Stability Bits

        58
      • FIGURE 4-3: Transition Timing From RC_RUN Mode to PRI_RUN Mode

        58
  • 4.3 Sleep Mode

    59
    • 4.3.1 Voltage Regulator Power Mode

      59
      • Register 4-1: VREGCON – Voltage Regulator Power Control Register(1)

        59
  • 4.4 Idle Modes

    60
    • FIGURE 4-4: Transition Timing for Entry to Sleep Mode

      60
    • FIGURE 4-5: Transition Timing for Wake from Sleep (HSPLL)

      60
    • 4.4.1 PRI_IDLE Mode

      60
    • 4.4.2 SEC_IDLE Mode

      61
      • FIGURE 4-6: Transition Timing for Entry to Idle Mode

        61
      • FIGURE 4-7: Transition Timing for Wake from Idle to Run Mode

        61
    • 4.4.3 RC_IDLE Mode

      62
  • 4.5 Exiting Idle and Sleep Modes

    62
    • 4.5.1 Exit by Interrupt

      62
    • 4.5.2 Exit by WDT Time-out

      62
    • 4.5.3 Exit by Reset

      63
    • 4.5.4 Exit without an Oscillator Start-up Delay

      63
  • 4.6 Selective Peripheral Module Control

    63
  • 4.7 Register Definitions: Peripheral Module Disable

    64
    • Register 4-2: PMD0: Peripheral Module Disable Register 0

      64
    • Register 4-3: PMD1: Peripheral Module Disable Register 1

      65
• 5.0 Reset

  67
  • 5.1 RCON Register

    67
    • FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit

      67
  • 5.2 Register Definitions: Reset Control

    68
    • Register 5-1: RCON: RESET Control Register

      68
  • 5.3 Master Clear (MCLR)

    69
  • 5.4 Power-on Reset (POR)

    69
    • FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)

      69
  • 5.5 Brown-out Reset (BOR)

    70
    • 5.5.1 Detecting BOR

      70
    • 5.5.2 Software Enabled BOR

      70
    • 5.5.3 Disabling BOR in Sleep Mode

      70
    • 5.5.4 Minimum BOR Enable Time

      70
      • TABLE 5-1: BOR Configurations

        71
  • 5.6 Low-Power BOR (LPBOR)

    71
  • 5.7 Device Reset Timers

    71
    • 5.7.1 Power-up Timer (PWRT)

      71
    • 5.7.2 Oscillator Start-up Timer (OST)

      71
    • 5.7.3 PLL Lock Time-out

      71
    • 5.7.4 Time-out Sequence

      71
      • TABLE 5-2: Time-out in Various Situations

        72
      • FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)

        72
      • FIGURE 5-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1

        72
      • FIGURE 5-5: Time-out Sequence on Power-up (Mclr not Tied to Vdd): Case 2

        73
      • FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)

        73
      • FIGURE 5-7: Time-out Sequence on Por w/PLL Enabled (MCLR Tied to Vdd)

        74
  • 5.8 Reset State of Registers

    75
    • TABLE 5-3: Status Bits, their Significance and the Initialization Condition for RCON Register

      75
    • TABLE 5-4: Registers Associated with Resets

      75
    • TABLE 5-5: Configuration Registers Associated with Resets

      76
• 6.0 Memory Organization

  77
  • 6.1 Program Memory Organization

    77
    • FIGURE 6-1: Program Memory Map and Stack for PIC18(L)F2X/45K50 Devices

      77
    • 6.1.1 Program Counter

      78
    • 6.1.2 Return Address Stack

      78
      • FIGURE 6-2: Return Address Stack and Associated Registers

        78
  • 6.2 Register Definitions: Stack Pointer

    80
    • Register 6-1: STKPTR: Stack Pointer Register

      80
    • 6.2.1 Stack Full and Underflow Resets

      80
    • 6.2.2 Fast Register Stack

      80
      • EXAMPLE 6-1: Fast Register Stack Code Example

        81
    • 6.2.3 Look-up Tables in Program Memory

      81
      • EXAMPLE 6-2: Computed GOTO Using an Offset Value

        81
  • 6.3 PIC18 Instruction Cycle

    82
    • 6.3.1 Clocking Scheme

      82
    • 6.3.2 Instruction Flow/Pipelining

      82
      • FIGURE 6-3: Clock/ Instruction Cycle

        82
      • EXAMPLE 6-3: Instruction Pipeline Flow

        82
    • 6.3.3 Instructions in Program Memory

      83
      • FIGURE 6-4: Instructions in Program Memory

        83
    • 6.3.4 Two-Word Instructions

      83
      • EXAMPLE 6-4: Two-Word Instructions

        83
  • 6.4 Data Memory Organization

    84
    • 6.4.1 USB RAM

      84
    • 6.4.2 Bank Select Register (BSR)

      84
      • FIGURE 6-5: Data Memory Map for PIC18(L)F2X/45K50 Devices

        85
      • FIGURE 6-6: Use of the Bank Select Register (Direct Addressing)

        86
    • 6.4.3 Access Bank

      87
    • 6.4.4 General Purpose Register File

      87
    • 6.4.5 Special Function Registers

      87
      • TABLE 6-1: Special Function Register Map for PIC18(L)F2X/45K50 Devices

        88
      • TABLE 6-2: Register File Summary for PIC18(L)F2X/45K50 Devices

        89
    • 6.4.6 Status Register

      93
  • 6.5 Register Definitions: Status

    93
    • Register 6-2: STATUS: STATUS Register

      93
  • 6.6 Data Addressing Modes

    94
    • 6.6.1 Inherent and Literal Addressing

      94
    • 6.6.2 Direct Addressing

      94
    • 6.6.3 Indirect Addressing

      94
      • EXAMPLE 6-5: How to Clear Ram (Bank 1) Using Indirect Addressing

        94
      • FIGURE 6-7: Indirect Addressing

        95
  • 6.7 Data Memory and the Extended Instruction Set

    96
    • 6.7.1 Indexed Addressing with Literal Offset

      96
    • 6.7.2 Instructions Affected by Indexed Literal Offset Mode

      96
      • FIGURE 6-8: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)

        97
    • 6.7.3 Mapping the Access Bank in Indexed Literal Offset Mode

      98
  • 6.8 PIC18 Instruction Execution and the Extended Instruction Set

    98
    • FIGURE 6-9: Remapping the Access Bank with Indexed Literal Offset Addressing

      98
• 7.0 Flash Program Memory

  99
  • 7.1 Table Reads and Table Writes

    99
    • FIGURE 7-1: Table Read Operation

      99
    • FIGURE 7-2: Table Write Operation

      100
  • 7.2 Control Registers

    100
    • 7.2.1 EECON1 and EECON2 Registers

      100
  • 7.3 Register Definitions: Memory Control

    101
    • Register 7-1: EECON1: Data EEPROM Control 1 Register

      101
    • 7.3.1 TABLAT – Table Latch Register

      102
    • 7.3.2 TBLPTR – Table Pointer Register

      102
    • 7.3.3 Table Pointer Boundaries

      102
      • TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        102
      • FIGURE 7-3: Table Pointer Boundaries Based on Operation

        102
  • 7.4 Reading the Flash Program Memory

    103
    • FIGURE 7-4: Reads from Flash Program Memory

      103
    • EXAMPLE 7-1: Reading a Flash Program Memory Word

      103
  • 7.5 Erasing Flash Program Memory

    104
    • 7.5.1 Flash Program Memory Erase Sequence

      104
      • EXAMPLE 7-2: Erasing a Flash Program Memory Block

        104
  • 7.6 Writing to Flash Program Memory

    105
    • FIGURE 7-5: Table Writes to Flash Program Memory

      105
    • 7.6.1 Flash Program Memory Write Sequence

      105
      • EXAMPLE 7-3: Writing to Flash Program Memory

        106
      • EXAMPLE 7-3: Writing to Flash Program Memory (Continued)

        107
    • 7.6.2 Write Verify

      107
    • 7.6.3 Unexpected Termination of Write Operation

      107
    • 7.6.4 Protection Against Spurious Writes

      107
  • 7.7 Flash Program Operation During Code Protection

    107
    • TABLE 7-2: Registers Associated with Program Flash Memory

      107
• 8.0 Data EEPROM Memory

  109
  • 8.1 EEADR Register

    109
  • 8.2 EECON1 and EECON2 Registers

    109
    • Register 8-1: EECON1: Data EEPROM Control 1 Register

      110
  • 8.3 Reading the Data EEPROM Memory

    111
  • 8.4 Writing to the Data EEPROM Memory

    111
  • 8.5 Write Verify

    111
    • EXAMPLE 8-1: Data EEPROM Read

      111
    • EXAMPLE 8-2: Data EEPROM Write

      111
  • 8.6 Operation During Code-Protect

    112
  • 8.7 Protection Against Spurious Write

    112
  • 8.8 Using the Data EEPROM

    112
    • EXAMPLE 8-3: Data EEPROM Refresh Routine

      112
    • TABLE 8-1: Registers Associated with Data EEPROM Memory

      113
• 9.0 8 X 8 Hardware Multiplier

  115
  • 9.1 Introduction

    115
  • 9.2 Operation

    115
    • EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine

      115
    • EXAMPLE 9-2: 8 x 8 Signed Multiply Routine

      115
    • TABLE 9-1: Performance Comparison for Various Multiply Operations

      115
    • EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm

      116
    • EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine

      116
    • EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm

      116
    • EXAMPLE 9-4: 16 x 16 Signed Multiply Routine

      116
• 10.0 Interrupts

  117
  • 10.1 Mid-Range Compatibility

    117
  • 10.2 Interrupt Priority

    117
  • 10.3 Interrupt Response

    117
    • FIGURE 10-1: PIC18 Interrupt Logic

      118
  • 10.4 INTCON Registers

    119
  • 10.5 PIR Registers

    119
  • 10.6 PIE Registers

    119
  • 10.7 IPR Registers

    119
  • 10.8 Register Definitions: Interrupt Control

    120
    • Register 10-1: INTCON: Interrupt Control Register

      120
    • Register 10-2: INTCON2: Interrupt Control 2 Register

      121
    • Register 10-3: INTCON3: Interrupt Control 3 Register

      122
    • Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1

      123
    • Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2

      124
    • Register 10-6: PIR3: Peripheral Interrupt (Flag) Register 3

      125
    • Register 10-7: PIE1: Peripheral Interrupt Enable (Flag) Register 1

      126
    • Register 10-8: PIE2: Peripheral Interrupt Enable (Flag) Register 2

      127
    • Register 10-9: PIE3: Peripheral Interrupt Enable (Flag) Register 3

      128
    • Register 10-10: IPR1: Peripheral Interrupt Priority Register 1

      129
    • Register 10-11: IPR2: Peripheral Interrupt Priority Register 2

      130
    • Register 10-12: IPR3: Peripheral Interrupt Priority Register 3

      131
  • 10.9 INTn Pin Interrupts

    132
  • 10.10 TMR0 Interrupt

    132
  • 10.11 PORTB/PORTC Interrupt-on- Change

    132
  • 10.12 Context Saving During Interrupts

    132
    • EXAMPLE 10-1: Saving Status, WREG and BSR Registers in RAM

      132
    • TABLE 10-1: Registers Associated with Interrupts

      133
    • TABLE 10-2: Configuration Registers Associated with Interrupts

      133
• 11.0 I/O Ports

  135
  • FIGURE 11-1: Generic I/O Port Operation

    135
  • 11.1 PORTA Registers

    135
    • EXAMPLE 11-1: Initializing PORTA

      135
    • TABLE 11-1: PORTA I/O Summary

      136
    • TABLE 11-2: Registers Associated with PORTA

      137
    • TABLE 11-3: Configuration Registers Associated with PORTA

      137
    • 11.1.1 PORTA Output Priority

      138
      • TABLE 11-4: Port Pin Function Priority

        139
  • 11.2 PORTB Registers

    140
    • EXAMPLE 11-2: Initializing PORTB

      140
    • 11.2.1 PORTB Output Priority

      140
  • 11.3 Additional PORTB Pin Functions

    140
    • 11.3.1 Weak Pull-Ups

      140
    • 11.3.2 Interrupt-On-Change

      140
    • 11.3.3 Alternate Functions

      141
      • TABLE 11-5: PORTB I/O Summary

        141
      • TABLE 11-6: Registers Associated with PORTB

        143
      • TABLE 11-7: Configuration Registers Associated with PORTB

        143
  • 11.4 PORTC Registers

    144
    • EXAMPLE 11-3: Initializing PORTC

      144
    • 11.4.1 PORTC Output Priority

      144
    • 11.4.2 Interrupt-on-Change

      144
      • TABLE 11-8: PORTC I/O Summary

        145
      • TABLE 11-9: Registers Associated with PORTC

        147
      • TABLE 11-10: Configuration Registers Associated with PORTC

        147
  • 11.5 PORTD Registers

    148
    • EXAMPLE 11-4: Initializing PORTD

      148
    • 11.5.1 PORTD Output Priority

      148
      • TABLE 11-11: PORTD I/O Summary

        149
      • TABLE 11-12: Registers Associated with PORTD

        150
  • 11.6 PORTE Registers

    151
    • 11.6.1 PORTE on 40/44-Pin Devices

      151
      • EXAMPLE 11-5: Initializing PORTE

        151
    • 11.6.2 PORTE on 28-Pin Devices

      151
    • 11.6.3 RE3 Weak Pull-Up

      151
    • 11.6.4 PORTE Output Priority

      151
      • TABLE 11-13: PORTE I/O Summary

        152
      • TABLE 11-14: Registers Associated with PORTE

        152
      • TABLE 11-15: Configuration Registers Associated with PORTE

        152
  • 11.7 Port Analog Control

    153
  • 11.8 Port Slew Rate Control

    153
  • 11.9 Register Definitions – Port Control

    153
    • Register 11-1: PORTx(1): PORTx Register

      153
    • Register 11-2: PORTE: PORTE Register

      154
    • Register 11-3: ANSELA – PORTA Analog Select Register

      154
    • Register 11-4: ANSELB – PORTB Analog Select Register

      155
    • Register 11-5: ANSELC – PORTC Analog Select Register

      155
    • Register 11-6: ANSELD – PORTD Analog Select Register

      155
    • Register 11-7: ANSELE – PORTE Analog Select Register

      156
    • Register 11-8: TRISx: PORTx Tri-State Register(1)

      156
    • Register 11-9: TRISE: PORTE Tri-State Register

      156
    • Register 11-10: LATx: Portx Output Latch Register(1)

      157
    • Register 11-11: LATE: PORTE Output Latch Register(1)

      157
    • Register 11-12: WPUB: Weak Pull-up PORTB Register

      157
    • Register 11-13: IOCB: Interrupt-on-Change PORTB Control register

      158
    • Register 11-14: IOCC: Interrupt-on-Change PORTC Control Register

      158
    • Register 11-15: SLRCON: Slew Rate Control Register

      159
• 12.0 Timer0 Module

  161
  • 12.1 Register Definitions: Timer0 Control

    161
    • Register 12-1: T0CON: Timer0 Control Register

      161
  • 12.2 Timer0 Operation

    162
  • 12.3 Timer0 Reads and Writes in 16-Bit Mode

    162
    • FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)

      162
    • FIGURE 12-2: Timer0 Block Diagram (16-Bit Mode)

      163
  • 12.4 Prescaler

    163
    • 12.4.1 Switching Prescaler Assignment

      163
  • 12.5 Timer0 Interrupt

    163
    • TABLE 12-1: Registers Associated with Timer0

      163
• 13.0 Timer1/3 Module with Gate Control

  165
  • FIGURE 13-1: Timer1/3 Block Diagram

    165
  • 13.1 Timer1/3 Operation

    166
    • TABLE 13-1: Timer1/3 Enable Selections

      166
  • 13.2 Clock Source Selection

    166
    • 13.2.1 Internal Clock Source

      166
    • 13.2.2 External Clock Source

      166
      • TABLE 13-2: Clock Source Selections

        166
  • 13.3 Timer1/3 Prescaler

    167
  • 13.4 Secondary Oscillator

    167
  • 13.5 Timer1/3 Operation in Asynchronous Counter Mode

    167
    • 13.5.1 Reading and Writing Timer1/3 in Asynchronous Counter Mode

      167
  • 13.6 Timer1/3 16-Bit Read/Write Mode

    167
    • FIGURE 13-2: Timer1/3 16-Bit Read/Write Mode Block Diagram

      168
  • 13.7 Timer1/3 Gate

    168
    • 13.7.1 Timer1/3 Gate Enable

      168
      • TABLE 13-3: Timer1/3 Gate Enable Selections

        168
    • 13.7.2 Timer1/3 Gate Source Selection

      168
      • TABLE 13-4: Timer1/3 Gate Sources

        168
    • 13.7.3 Timer1/3 Gate Toggle Mode

      169
    • 13.7.4 Timer1/3 Gate Single-Pulse Mode

      169
    • 13.7.5 Timer1/3 Gate Value Status

      169
    • 13.7.6 Timer1/3 Gate Event Interrupt

      169
  • 13.8 Timer1/3 Interrupt

    170
  • 13.9 Timer1/3 Operation During Sleep

    170
  • 13.10 ECCP/CCP Capture/Compare Time Base

    170
  • 13.11 ECCP/CCP Special Event Trigger

    170
    • FIGURE 13-3: Timer1/3 Incrementing Edge

      171
    • FIGURE 13-4: Timer1/3 Gate Enable Mode

      171
    • FIGURE 13-5: Timer1/3 Gate Toggle Mode

      172
    • FIGURE 13-6: Timer1/3 Gate Single-Pulse Mode

      172
    • FIGURE 13-7: Timer1/3 Gate Single-Pulse and Toggle Combined Mode

      173
  • 13.12 Peripheral Module Disable

    173
  • 13.13 Register Definitions: Timer1/3 Control

    174
    • Register 13-1: TxCON: Timer1/3 Control Register

      174
    • Register 13-2: TxGCON: Timer1/3 Gate Control Register

      175
    • TABLE 13-5: Registers Associated with Timer1/3 as a Timer/Counter

      176
    • TABLE 13-6: Configuration Registers Associated with Timer1/3

      176
• 14.0 Timer2 Module

  177
  • FIGURE 14-1: Timer2 Block Diagram

    177
  • 14.1 Timer2 Operation

    178
  • 14.2 Timer2 Interrupt

    178
  • 14.3 Timer2 Output

    178
  • 14.4 Timer2 Operation During Sleep

    178
  • 14.5 Peripheral Module Disable

    178
  • 14.6 Register Definitions: Timer2 Control

    179
    • Register 14-1: T2CON: Timer2 Control Register

      179
    • TABLE 14-1: Summary of Registers Associated With Timer2

      180
• 15.0 Capture/Compare/PWM Modules

  181
  • 15.1 Capture Mode

    181
    • FIGURE 15-1: Capture Mode Operation Block Diagram

      181
    • 15.1.1 CCP pin Configuration

      182
      • TABLE 15-1: CCP Pin Multiplexing

        182
    • 15.1.2 Timer1 Mode Resource

      182
    • 15.1.3 Software Interrupt Mode

      182
    • 15.1.4 CCP Prescaler

      183
      • EXAMPLE 15-1: Changing Between Capture Prescalers

        183
    • 15.1.5 Capture During Sleep

      183
      • TABLE 15-2: Registers Associated with Capture

        184
      • TABLE 15-3: Configuration Registers Associated with Capture

        184
  • 15.2 Compare Mode

    185
    • FIGURE 15-2: Compare Mode Operation Block Diagram

      185
    • 15.2.1 CCP Pin Configuration

      185
    • 15.2.2 Timerx Mode Resource

      185
    • 15.2.3 Software Interrupt Mode

      185
    • 15.2.4 Special Event Trigger

      186
    • 15.2.5 Compare During Sleep

      186
      • TABLE 15-4: Registers Associated with Compare

        187
      • TABLE 15-5: Configuration Registers Associated with Capture

        187
  • 15.3 PWM Overview

    188
    • 15.3.1 Standard PWM Operation

      188
      • FIGURE 15-3: CCP PWM Output Signal

        188
      • FIGURE 15-4: Simplified PWM Block Diagram

        188
    • 15.3.2 Setup for PWM Operation

      188
    • 15.3.3 PWM Period

      189
      • EQUATION 15-1: PWM Period

        189
    • 15.3.4 PWM Duty Cycle

      189
      • EQUATION 15-2: Pulse Width

        189
      • EQUATION 15-3: Duty Cycle Ratio

        189
    • 15.3.5 PWM Resolution

      190
      • EQUATION 15-4: PWM Resolution

        190
      • TABLE 15-6: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)

        190
      • TABLE 15-7: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)

        190
      • TABLE 15-8: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)

        190
    • 15.3.6 Operation in Sleep Mode

      190
    • 15.3.7 Changes in System Clock Frequency

      190
    • 15.3.8 Effects of Reset

      190
      • TABLE 15-9: Registers Associated with Standard PWM

        191
      • TABLE 15-10: Configuration Registers Associated with Capture

        191
  • 15.4 PWM (Enhanced Mode)

    192
    • FIGURE 15-5: Example Simplified Block Diagram of the Enhanced PWM Mode

      192
    • TABLE 15-11: Example Pin Assignments for Various PWM Enhanced Modes

      193
    • FIGURE 15-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)

      193
    • FIGURE 15-7: Example Enhanced PWM Output Relationships (Active-Low State)

      194
    • 15.4.1 Half-Bridge Mode

      195
      • FIGURE 15-8: Example of Half- Bridge PWM Output

        195
      • FIGURE 15-9: Example of Half-Bridge Applications

        195
    • 15.4.2 Full-Bridge Mode

      196
      • FIGURE 15-10: Example of Full-Bridge Application

        196
      • FIGURE 15-11: Example of Full-Bridge PWM Output

        197
      • FIGURE 15-12: Example of PWM Direction Change

        198
      • FIGURE 15-13: Example of PWM Direction Change at Near 100% Duty Cycle

        199
    • 15.4.3 Enhanced PWM Auto- shutdown Mode

      199
      • FIGURE 15-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        200
    • 15.4.4 Auto-Restart Mode

      200
      • FIGURE 15-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)

        200
    • 15.4.5 Programmable Dead-Band Delay Mode

      201
      • FIGURE 15-16: Example of Half- Bridge PWM Output

        201
      • FIGURE 15-17: Example of Half-Bridge Applications

        201
    • 15.4.6 PWM Steering Mode

      202
      • FIGURE 15-18: Simplified Steering Block Diagram

        202
    • 15.4.7 Start-up Considerations

      203
      • FIGURE 15-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)

        203
      • FIGURE 15-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)

        203
    • 15.4.8 Setup for ECCP PWM Operation using ECCP1 and Timer2

      204
      • TABLE 15-12: Registers Associated with Enhanced PWM

        205
  • 15.5 Register Definitions: ECCP Control

    206
    • Register 15-1: CCPXCON: Standard CCPx Control Register

      206
    • Register 15-2: CCPxCON: Enhanced CCPx Control Register

      207
    • Register 15-3: CCPTMRS: PWM Timer Selection Control Register 0

      209
    • Register 15-4: ECCPxAS: CCPx Auto-Shutdown Control Register

      210
    • Register 15-5: PWMxCON: Enhanced PWM Control Register

      211
    • Register 15-6: PSTRxCON: PWM Steering Control Register(1)

      211
• 16.0 Master Synchronous Serial Port (MSSP) Module

  213
  • 16.1 Module Overview

    213
    • FIGURE 16-1: MSSP Block Diagram (SPI mode)

      213
    • FIGURE 16-2: MSSP Block Diagram (I2C™ Master mode)

      214
    • FIGURE 16-3: MSSP Block Diagram (I2C™ Slave mode)

      215
  • 16.2 SPI Mode Overview

    216
    • FIGURE 16-4: SPI Master and Multiple Slave Connection

      217
    • 16.2.1 SPI Mode Registers

      217
    • 16.2.2 SPI Mode Operation

      217
      • FIGURE 16-5: SPI Master/Slave Connection

        218
    • 16.2.3 SPI Master Mode

      219
      • FIGURE 16-6: SPI Mode Waveform (Master Mode)

        219
    • 16.2.4 SPI Slave Mode

      220
    • 16.2.5 Slave Select Synchronization

      220
      • FIGURE 16-7: SPI Daisy-Chain Connection

        221
      • FIGURE 16-8: Slave Select Synchronous Waveform

        221
      • FIGURE 16-9: SPI Mode Waveform (Slave Mode With CKE = 0)

        222
      • FIGURE 16-10: SPI Mode Waveform (SLAve Mode With CKE = 1)

        222
    • 16.2.6 SPI Operation IN Sleep Mode

      223
      • TABLE 16-1: Registers Associated with SPI Operation

        223
  • 16.3 I2C Mode Overview

    224
    • FIGURE 16-11: I2C™ Master/ Slave Connection

      224
    • 16.3.1 Clock Stretching

      225
    • 16.3.2 Arbitration

      225
  • 16.4 I2C Mode Operation

    226
    • 16.4.1 Byte Format

      226
    • 16.4.2 Definition of I2C Terminology

      226
    • 16.4.3 SDA and SCL Pins

      226
    • 16.4.4 SDA Hold Time

      226
      • TABLE 16-2: I2C™ Bus Terms

        226
    • 16.4.5 Start Condition

      227
    • 16.4.6 STOP Condition

      227
    • 16.4.7 Restart Condition

      227
    • 16.4.8 START/STOP Condition Interrupt Masking

      227
      • FIGURE 16-12: I2C™ START and STOP Conditions

        227
      • FIGURE 16-13: I2C™ Restart Condition

        227
    • 16.4.9 Acknowledge Sequence

      228
  • 16.5 I2C Slave Mode Operation

    228
    • 16.5.1 Slave Mode Addresses

      228
    • 16.5.2 Slave Reception

      229
      • FIGURE 16-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)

        230
      • FIGURE 16-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        231
      • FIGURE 16-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)

        232
      • FIGURE 16-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)

        233
    • 16.5.3 SLAVE Transmission

      234
      • FIGURE 16-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)

        235
      • FIGURE 16-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)

        237
    • 16.5.4 Slave Mode 10-bit Address Reception

      238
    • 16.5.5 10-bit Addressing With Address Or Data Hold

      238
      • FIGURE 16-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        239
      • FIGURE 16-21: I2C Slave, 10-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0)

        240
      • FIGURE 16-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)

        241
    • 16.5.6 Clock Stretching

      242
    • 16.5.7 Clock Synchronization and the CKP bit

      242
      • FIGURE 16-23: Clock Synchronization Timing

        242
    • 16.5.8 General Call Address Support

      243
      • FIGURE 16-24: Slave Mode General Call Address Sequence

        243
    • 16.5.9 SSPx Mask Register

      243
  • 16.6 I2C Master Mode

    244
    • 16.6.1 I2C Master Mode Operation

      244
    • 16.6.2 Clock Arbitration

      245
      • FIGURE 16-25: Baud Rate Generator Timing with Clock Arbitration

        245
    • 16.6.3 WCOL Status Flag

      245
    • 16.6.4 I2C Master Mode Start Condition Timing

      246
      • FIGURE 16-26: First Start Bit Timing

        246
    • 16.6.5 I2C Master Mode Repeated Start Condition Timing

      247
      • FIGURE 16-27: Repeat Start Condition Waveform

        247
    • 16.6.6 I2C Master Mode Transmission

      248
      • FIGURE 16-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)

        249
    • 16.6.7 I2C Master Mode Reception

      250
      • FIGURE 16-29: I2C™ Master Mode Waveform (Reception, 7-Bit Address)

        251
    • 16.6.8 Acknowledge Sequence Timing

      252
    • 16.6.9 Stop Condition Timing

      252
      • FIGURE 16-30: Acknowledge Sequence Waveform

        252
      • FIGURE 16-31: Stop Condition Receive or Transmit Mode

        252
    • 16.6.10 Sleep Operation

      253
    • 16.6.11 Effects of a Reset

      253
    • 16.6.12 Multi-Master Mode

      253
    • 16.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration

      254
      • FIGURE 16-32: Bus Collision Timing for Transmit and Acknowledge

        254
      • FIGURE 16-33: Bus Collision During Start Condition (SDA Only)

        255
      • FIGURE 16-34: Bus Collision During Start Condition (SCL = 0)

        256
      • FIGURE 16-35: BRG Reset Due to Sda Arbitration During Start Condition

        256
      • FIGURE 16-36: Bus Collision During a Repeated Start Condition (Case 1)

        257
      • FIGURE 16-37: Bus Collision During Repeated Start Condition (Case 2)

        257
      • FIGURE 16-38: Bus Collision During a Stop Condition (Case 1)

        258
      • FIGURE 16-39: Bus Collision During a Stop Condition (Case 2)

        258
      • TABLE 16-3: Registers Associated with I2C™ Operation

        259
  • 16.7 Baud Rate Generator

    260
    • FIGURE 16-40: Baud Rate Generator Block Diagram

      260
    • TABLE 16-4: MSSP Clock Rate w/BRG

      260
  • 16.8 Register Definitions: MSSP Control

    261
    • Register 16-1: SSPxSTAT: SSPx STATUS Register

      261
    • Register 16-2: SSPxCON1: SSPx Control Register 1

      262
    • Register 16-3: SSPxCON2: SSPx Control Register 2

      264
    • Register 16-4: SSPxCON3: SSPx Control Register 3

      265
    • Register 16-5: SSPxMSK: SSPx Mask Register

      266
    • Register 16-6: SSPxADD: MSSP Address and Baud Rate Register (I2C Mode)

      267
• 17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  269
  • FIGURE 17-1: EUSART Transmit Block Diagram

    269
  • FIGURE 17-2: EUSART Receive Block Diagram

    270
  • 17.1 EUSART Asynchronous Mode

    271
    • 17.1.1 EUSART Asynchronous Transmitter

      271
      • FIGURE 17-3: Asynchronous Transmission

        272
      • FIGURE 17-4: Asynchronous Transmission (Back-to-Back)

        273
      • TABLE 17-1: Registers Associated with Asynchronous Transmission

        273
    • 17.1.2 EUSART Asynchronous Receiver

      274
      • FIGURE 17-5: Asynchronous Reception

        277
      • TABLE 17-2: Registers Associated with Asynchronous Reception

        277
  • 17.2 Clock Accuracy with Asynchronous Operation

    278
  • 17.3 Register Definitions: EUSART Control

    279
    • Register 17-1: TXSTAx: Transmit Status and Control Register

      279
    • Register 17-2: RCSTAx: Receive Status and Control Register

      280
    • Register 17-3: BAUDCONx: Baud Rate Control Register

      281
  • 17.4 EUSART Baud Rate Generator (BRG)

    282
    • EXAMPLE 17-1: Calculating Baud Rate Error

      282
    • TABLE 17-3: Baud Rate Formulas

      282
    • TABLE 17-4: Registers Associated with Baud Rate Generator

      283
    • TABLE 17-5: BAUD Rates for Asynchronous Modes

      283
    • 17.4.1 Auto-Baud Detect

      286
      • TABLE 17-6: BRG Counter Clock Rates

        286
      • FIGURE 17-6: Automatic Baud Rate Calibration

        286
    • 17.4.2 Auto-baud Overflow

      287
    • 17.4.3 Auto-Wake-up on Break

      287
      • FIGURE 17-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation

        288
      • FIGURE 17-8: Auto-Wake-up Bit (WUE) Timings During Sleep

        288
    • 17.4.4 BREAK Character Sequence

      289
    • 17.4.5 Receiving a BREAK Character

      289
      • FIGURE 17-9: Send Break Character Sequence

        289
  • 17.5 EUSART Synchronous Mode

    290
    • 17.5.1 Synchronous Master Mode

      290
      • FIGURE 17-10: Synchronous Transmission

        291
      • FIGURE 17-11: Synchronous Transmission (Through TXEN)

        291
      • TABLE 17-7: Registers Associated with Synchronous Master Transmission

        292
      • FIGURE 17-12: Synchronous Reception (Master Mode, SREN)

        294
      • TABLE 17-8: Registers Associated with Synchronous Master Reception

        294
    • 17.5.2 Synchronous Slave Mode

      295
      • TABLE 17-9: Registers Associated with Synchronous Slave Transmission

        296
      • TABLE 17-10: Registers Associated with Synchronous Slave Reception

        297
• 18.0 Analog-to-Digital Converter (ADC) Module

  299
  • FIGURE 18-1: ADC Block Diagram

    299
  • 18.1 ADC Configuration

    300
    • 18.1.1 Port Configuration

      300
    • 18.1.2 Channel Selection

      300
    • 18.1.3 ADC Voltage Reference

      300
    • 18.1.4 Selecting and Configuring Acquisition Time

      300
    • 18.1.5 Conversion Clock

      301
    • 18.1.6 Interrupts

      301
      • TABLE 18-1: ADC Clock Period (Tad) vs. Device Operating Frequencies

        301
    • 18.1.7 Result Formatting

      302
      • FIGURE 18-2: 10-Bit A/D Conversion Result Format

        302
  • 18.2 ADC Operation

    303
    • 18.2.1 Starting a Conversion

      303
      • FIGURE 18-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, TACQ = 0)

        303
      • FIGURE 18-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, TACQ = 4 TAD)

        303
    • 18.2.2 Completion of a Conversion

      304
    • 18.2.3 Discharge

      304
    • 18.2.4 Terminating a Conversion

      304
    • 18.2.5 Delay Between Conversions

      304
    • 18.2.6 ADC Operation in Power- Managed Modes

      304
    • 18.2.7 ADC Operation During Sleep

      304
    • 18.2.8 Special Event Trigger

      304
    • 18.2.9 Peripheral Module Disable

      304
    • 18.2.10 A/D Conversion Procedure

      305
      • EXAMPLE 18-1: A/D Conversion

        305
  • 18.3 Register Definitions: ADC Control

    306
    • Register 18-1: ADCON0: A/D Control Register 0

      306
    • Register 18-2: ADCON1: A/D Control Register 1

      307
    • Register 18-3: ADCON2: A/D Control Register 2

      308
    • Register 18-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0

      309
    • Register 18-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0

      309
    • Register 18-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1

      309
    • Register 18-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1

      309
  • 18.4 A/D Acquisition Requirements

    310
    • EQUATION 18-1: Acquisition Time Example

      310
    • FIGURE 18-5: Analog Input Model

      311
    • FIGURE 18-6: ADC Transfer Function

      311
    • TABLE 18-2: Registers Associated with A/D Operation

      312
    • TABLE 18-3: Configuration Registers Associated with the ADC Module

      312
• 19.0 Comparator Module

  313
  • 19.1 Comparator Overview

    313
    • FIGURE 19-1: Single Comparator

      313
    • FIGURE 19-2: Comparator C1/C2 Simplified Block Diagram

      314
  • 19.2 Comparator Control

    315
    • 19.2.1 Comparator Enable

      315
    • 19.2.2 Comparator Input Selection

      315
    • 19.2.3 Comparator Reference Selection

      315
    • 19.2.4 Comparator Output Selection

      315
    • 19.2.5 Comparator Output Polarity

      315
      • TABLE 19-1: Comparator Output State vs. Input Conditions

        315
    • 19.2.6 Comparator Speed Selection

      315
  • 19.3 Comparator Response Time

    315
  • 19.4 Comparator Interrupt Operation

    316
    • 19.4.1 Presetting the Mismatch Latches

      316
      • FIGURE 19-3: Comparator Interrupt Timing W/O CMxCON0 Read

        316
      • FIGURE 19-4: Comparator Interrupt Timing With CMxCON0 Read

        316
  • 19.5 Operation During Sleep

    317
  • 19.6 Effects of a Reset

    317
  • 19.7 Analog Input Connection Considerations

    317
    • FIGURE 19-5: Analog Input Model

      317
  • 19.8 Additional Comparator Features

    318
    • 19.8.1 Simultaneous Comparator Output Read

      318
    • 19.8.2 Internal Reference Selection

      318
    • 19.8.3 Synchronizing Comparator Output to Timer1

      318
  • 19.9 Register Definitions: Comparator Control

    319
    • Register 19-1: CMxCON0: Comparator x Control Register

      319
    • Register 19-2: CM2CON1: Comparator 1 and 2 Control Register

      320
    • TABLE 19-2: Registers Associated with Comparator Module

      321
• 20.0 Charge Time Measurement Unit (CTMU)

  323
  • FIGURE 20-1: CTMU Block Diagram

    323
  • 20.1 CTMU Operation

    324
    • 20.1.1 Theory of Operation

      324
    • 20.1.2 Current Source

      324
    • 20.1.3 Edge Selection and Control

      324
    • 20.1.4 Edge Status

      325
    • 20.1.5 Interrupts

      325
  • 20.2 CTMU Module Initialization

    325
  • 20.3 Calibrating the CTMU Module

    326
    • 20.3.1 Current Source Calibration

      326
      • FIGURE 20-2: CTMU Current Source Calibration Circuit

        326
      • EXAMPLE 20-1: Setup for CTMU Calibration Routines

        327
      • EXAMPLE 20-2: Current Calibration Routine

        328
    • 20.3.2 Capacitance Calibration

      329
      • EXAMPLE 20-3: Capacitance Calibration Routine

        330
  • 20.4 Measuring Capacitance with the CTMU

    331
    • 20.4.1 Absolute Capacitance Measurement

      331
    • 20.4.2 Relative Charge Measurement

      331
      • EXAMPLE 20-4: Routine for Capacitive Touch Switch

        332
  • 20.5 Measuring Time with the CTMU Module

    333
    • FIGURE 20-3: Typical Connections and Internal Configuration for Time Measurement

      333
  • 20.6 Creating a Delay with the CTMU Module

    334
    • FIGURE 20-4: Typical Connections and Internal Configuration for Pulse Delay Generation

      334
  • 20.7 Operation During Sleep/Idle Modes

    334
    • 20.7.1 Sleep Mode

      334
    • 20.7.2 Idle Mode

      334
  • 20.8 CTMU Peripheral Module Disable (PMD)

    334
  • 20.9 Effects of a Reset on CTMU

    335
  • 20.10 Registers

    335
  • 20.11 Register Definitions: CTMU Control

    335
    • Register 20-1: CTMUCONH: CTMU Control Register 0

      335
    • Register 20-2: CTMUCONL: CTMU Control Register 1

      336
    • Register 20-3: CTMUICON: CTMU Current Control Register

      337
    • TABLE 20-1: Registers Associated with CTMU Module

      337
• 21.0 SR Latch

  339
  • 21.1 Latch Operation

    339
  • 21.2 Latch Output

    339
  • 21.3 DIVSRCLK Clock Generation

    339
  • 21.4 Effects of a Reset

    339
    • FIGURE 21-1: DIVSRCLK Block Diagram

      340
    • FIGURE 21-2: SR Latch Simplified Block Diagram

      340
    • TABLE 21-1: DIVSRCLK Frequency Table

      341
  • 21.5 Register Definitions: SR Latch Control

    342
    • Register 21-1: SRCON0: SR Latch Control Register

      342
    • Register 21-2: SRCON1: SR Latch Control Register 1

      343
    • TABLE 21-2: Registers Associated with the SR Latch

      343
• 22.0 Fixed Voltage Reference (FVR)

  345
  • 22.1 Independent Gain Amplifiers

    345
  • 22.2 FVR Stabilization Period

    345
    • FIGURE 22-1: Voltage Reference Block Diagram

      345
  • 22.3 Register Definitions: FVR Control

    346
    • Register 22-1: VREFCON0: Fixed Voltage Reference Control Register

      346
    • TABLE 22-1: Summary of Registers Associated with Fixed Voltage Reference

      346
• 23.0 Digital-to-Analog Converter (DAC) Module

  347
  • 23.1 Output Voltage Selection

    347
    • EQUATION 23-1: DAC Output Voltage

      347
  • 23.2 Ratiometric Output Level

    347
  • 23.3 Low-Power Voltage State

    347
  • 23.4 Output Clamped to Positive Voltage Source

    347
  • 23.5 Output Clamped to Negative Voltage Source

    347
  • 23.6 DAC Voltage Reference Output

    347
    • FIGURE 23-1: Digital-to-Analog Converter Block Diagram

      348
    • FIGURE 23-2: Voltage Reference Output Buffer Example

      348
  • 23.7 Operation During Sleep

    349
  • 23.8 Effects of a Reset

    349
  • 23.9 Register Definitions: DAC Control

    349
    • Register 23-1: VREFCON1: Voltage Reference Control Register 0

      349
    • Register 23-2: VREFCON2: Voltage Reference Control Register 1

      350
    • TABLE 23-1: Registers Associated with DAC Module

      350
• 24.0 Universal Serial Bus (USB)

  351
  • 24.1 Overview of the USB Peripheral

    351
    • FIGURE 24-1: USB Peripheral and Options

      351
  • 24.2 USB Status and Control

    352
    • 24.2.1 USB Control Register (UCON)

      352
      • Register 24-1: UCON: USB Control Register

        353
    • 24.2.2 USB Configuration Register (UCFG)

      354
      • Register 24-2: UCFG: USB Configuration Register (Banked F39h)

        355
      • FIGURE 24-2: External Circuitry

        356
    • 24.2.3 USB Status Register (USTAT)

      357
      • FIGURE 24-3: USTAT FIFO

        357
      • Register 24-3: USTAT: USB Status Register (Access F64h)

        357
    • 24.2.4 USB Endpoint Control

      358
      • Register 24-4: UEPn: USB Endpoint n Control Register (UEP0 Through UEP15)

        358
    • 24.2.5 USB Address Register (UADDR)

      359
    • 24.2.6 USB Frame Number Registers (UFRMH:UFRML)

      359
  • 24.3 USB RAM

    359
    • FIGURE 24-4: Implementation of USB RAM in Data Memory Space

      359
  • 24.4 Buffer Descriptors and the Buffer Descriptor Table

    360
    • 24.4.1 BD Status and Configuration

      360
      • FIGURE 24-5: Example of a Buffer Descriptor

        360
      • TABLE 24-1: Effect of DTSEN Bit on Odd/Even (DATA0/DATA1) Packet Reception

        361
      • Register 24-5: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), CPU Mode (Banked 4xxh)

        362
    • 24.4.2 BD Byte Count

      363
    • 24.4.3 BD Address Validation

      363
      • Register 24-6: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), SIE Mode (Data Returned By the Side to the MCU)

        363
    • 24.4.4 Ping-Pong Buffering

      364
      • FIGURE 24-6: Buffer Descriptor Table Mapping for Buffering Modes

        364
      • TABLE 24-2: Assignment of Buffer Descriptors for the Different Buffering Modes

        365
      • TABLE 24-3: Summary of USB Buffer Descriptor Table Registers

        365
  • 24.5 USB Interrupts

    366
    • FIGURE 24-7: USB Interrupt Logic Funnel

      366
    • FIGURE 24-8: Example of a USB Transaction and Interrupt Events

      366
    • 24.5.1 USB Interrupt Status Register (UIR)

      367
      • Register 24-7: UIR: USB Interrupt Status Register

        367
      • EXAMPLE 24-1: Clearing ACTVIF Bit (UIR<2>)

        368
    • 24.5.2 USB Interrupt Enable Register (UIE)

      369
      • Register 24-8: UIE: USB Interrupt Enable Register

        369
    • 24.5.3 USB Error Interrupt Status Register (UEIR)

      370
      • Register 24-9: UEIR: USB Error Interrupt Status Register

        370
    • 24.5.4 USB Error Interrupt Enable Register (UEIE)

      371
      • Register 24-10: UEIE: USB Error Interrupt Enable Register

        371
  • 24.6 USB Power Modes

    372
    • 24.6.1 Bus Power Only

      372
      • FIGURE 24-9: Bus Power Only

        372
    • 24.6.2 Self-Power Only

      372
      • FIGURE 24-10: Self-Power Only

        372
    • 24.6.3 Dual Power with Self-Power Dominance

      373
      • FIGURE 24-11: Dual Power Example

        373
    • 24.6.4 USB Transceiver Current Consumption

      373
      • EQUATION 24-1: Estimating USB Transceiver Current Consumption

        374
      • EXAMPLE 24-2: Calculating USB Transceiver Current†

        374
  • 24.7 Oscillator

    375
  • 24.8 Interrupt-On-Change for D+/D- pins

    375
  • 24.9 USB Firmware and Drivers

    375
    • TABLE 24-4: Registers Associated with USB Module Operation(1)

      376
  • 24.10 Overview of USB

    377
    • 24.10.1 Layered Framework

      377
    • 24.10.2 Frames

      377
    • 24.10.3 Transfers

      377
    • 24.10.4 Power

      377
      • FIGURE 24-12: USB Layers

        377
    • 24.10.5 Enumeration

      378
    • 24.10.6 Descriptors

      378
    • 24.10.7 Bus Speed

      378
    • 24.10.8 Class Specifications and Drivers

      378
• 25.0 High/Low-Voltage Detect (HLVD)

  379
  • 25.1 Register – HLVD Control

    379
    • Register 25-1: HLVDCON: High/Low-Voltage Detect Control Register

      379
  • 25.2 Operation

    380
    • FIGURE 25-1: HLVD Module Block Diagram (with External Input)

      380
  • 25.3 HLVD Setup

    381
  • 25.4 Current Consumption

    381
  • 25.5 HLVD Start-up Time

    381
    • FIGURE 25-2: Low-Voltage Detect Operation (VDIRMAG = 0)

      381
    • FIGURE 25-3: High-Voltage Detect Operation (VDIRMAG = 1)

      382
  • 25.6 Applications

    382
    • FIGURE 25-4: Typical Low-Voltage Detect Application

      382
  • 25.7 Operation During Sleep

    383
  • 25.8 Effects of a Reset

    383
    • TABLE 25-1: Registers Associated with High/Low-Voltage Detect Module

      383
• 26.0 Special Features of the CPU

  385
  • 26.1 Configuration Bits

    385
    • TABLE 26-1: Configuration Bits and Device IDs

      386
  • 26.2 Register Definitions: Configuration Word

    387
    • Register 26-1: CONFIG1L: Configuration Register 1 Low

      387
    • Register 26-2: CONFIG1H: Configuration Register 1 High

      388
    • Register 26-3: CONFIG2L: Configuration Register 2 Low

      389
    • Register 26-4: CONFIG2H: Configuration Register 2 High

      390
    • Register 26-5: CONFIG3H: Configuration Register 3 High

      391
    • Register 26-6: CONFIG4L: Configuration Register 4 Low

      392
    • Register 26-7: CONFIG5L: Configuration Register 5 Low

      393
    • Register 26-8: CONFIG5H: Configuration Register 5 High

      393
    • Register 26-9: CONFIG6L: Configuration Register 6 Low

      394
    • Register 26-10: CONFIG6H: Configuration Register 6 High

      395
    • Register 26-11: CONFIG7L: Configuration Register 7 Low

      395
    • Register 26-12: CONFIG7H: Configuration Register 7 High

      396
    • Register 26-13: DEVID1: Device ID Register 1

      396
    • Register 26-14: DEVID2: Device ID Register 2

      396
    • TABLE 26-2: Device ID Table for the PIC18(L)F2X/45K50 Family

      397
  • 26.3 Watchdog Timer (WDT)

    398
    • FIGURE 26-1: WDT Block Diagram

      398
    • 26.3.1 Control Register

      399
  • 26.4 Register Definitions: WDT Control

    399
    • Register 26-15: WDTCON: Watchdog Timer Control Register

      399
    • TABLE 26-3: Registers Associated with Watchdog Timer

      399
    • TABLE 26-4: Configuration Registers Associated with Watchdog Timer

      399
  • 26.5 Program Verification and Code Protection

    400
    • FIGURE 26-2: Code-Protected Program Memory for PIC18(L)F2X/45K50

      400
    • TABLE 26-5: Configuration Registers Associated with Code Protection

      400
    • 26.5.1 Program Memory Code Protection

      401
      • FIGURE 26-3: Table Write (WRTn) Disallowed

        401
      • FIGURE 26-4: External Block Table Read (EBTRn) Disallowed

        402
      • FIGURE 26-5: Internal Block Table Read (EBTRn) Allowed

        402
    • 26.5.2 Data EEPROM Code Protection

      403
    • 26.5.3 Configuration Register Protection

      403
  • 26.6 ID Locations

    403
  • 26.7 In-Circuit Serial Programming

    403
  • 26.8 In-Circuit Debugger

    403
    • TABLE 26-6: Debugger Resources

      403
  • 26.9 Special ICPORT Features (44-Pin TQFP Package Only)

    403
    • 26.9.1 Dedicated ICD/ICSP Port

      403
      • TABLE 26-7: Equivalent Pins for Legacy and Dedicated ICD/ICSP™ Ports

        403
  • 26.10 Single-Supply ICSP Programming

    404
• 27.0 Instruction Set Summary

  405
  • 27.1 Standard Instruction Set

    405
    • TABLE 27-1: Opcode Field Descriptions

      406
    • FIGURE 27-1: General Format for Instructions

      407
    • TABLE 27-2: PIC18 Instruction Set

      408
    • 27.1.1 Standard Instruction Set

      411
  • 27.2 Extended Instruction Set

    447
    • 27.2.1 Extended Instruction Syntax

      447
      • TABLE 27-3: Extensions to the PIC18 Instruction Set

        447
    • 27.2.2 Extended Instruction Set

      448
    • 27.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode

      452
    • 27.2.4 Considerations when Enabling the Extended Instruction Set

      452
    • 27.2.5 Special Considerations with Microchip MPLAB® IDE Tools

      454
• 28.0 Development Support

  455
• 29.0 Electrical Characteristics

  459
  • Absolute Maximum Ratings (†)

    459
    • FIGURE 29-1: PIC18LF2X/45K50 Family Voltage-Frequency Graph (Industrial Temperature)

      460
    • FIGURE 29-2: PIC18F2X/45K50 Family Voltage-Frequency Graph (Industrial Temperature)

      460
  • 29.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/45K50

    461
  • 29.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/45K50

    462
  • 29.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/45K50

    464
  • 29.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/45K50

    466
  • 29.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/45K50

    468
  • 29.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/45K50

    469
  • 29.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/45K50

    470
  • 29.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/45K50

    472
  • 29.9 Memory Programming Requirements

    474
  • 29.10 USB Module Specifications

    475
  • 29.11 Analog Characteristics

    476
    • TABLE 29-1: Comparator Specifications

      476
    • TABLE 29-2: DIGITAL-TO-ANALOG CONVERTER (DAC) Specifications

      476
    • TABLE 29-3: Fixed Voltage Reference (FVR) Specifications

      477
    • TABLE 29-4: Charge Time Measurement Unit (CTMU) Specifications

      477
    • FIGURE 29-3: High/Low-Voltage Detect Characteristics

      477
    • TABLE 29-5: High/Low-Voltage Detect Characteristics

      478
  • 29.12 AC (Timing) Characteristics

    479
    • 29.12.1 Timing Parameter Symbology

      479
    • 29.12.2 Timing Conditions

      480
      • TABLE 29-6: Temperature and Voltage Specifications – AC

        480
      • FIGURE 29-4: Load Conditions for Device Timing Specifications

        480
    • 29.12.3 Timing Diagrams and Specifications

      481
      • FIGURE 29-5: External Clock Timing (All Modes Except PLL)

        481
      • TABLE 29-7: External Clock Timing Requirements

        481
      • TABLE 29-8: PLL Clock Timing Specifications

        482
      • TABLE 29-9: AC Characteristics: Internal Oscillators Accuracy (PIC18(L)F2X/45K50)

        482
      • FIGURE 29-6: CLKO and I/O Timing

        483
      • TABLE 29-10: CLKO and I/O Timing Requirements

        483
      • FIGURE 29-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        484
      • FIGURE 29-8: Brown-out Reset Timing

        484
      • TABLE 29-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements

        485
      • FIGURE 29-9: Timer0 and Timer1 External Clock Timings

        485
      • TABLE 29-12: Timer0 and Timer1/3 External Clock Requirements

        486
      • FIGURE 29-10: Capture/Compare/PWM Timings (All CCP Modules)

        486
      • TABLE 29-13: Capture/Compare/PWM Requirements (All CCP Modules)

        487
      • FIGURE 29-11: Example SPI Master Mode Timing (CKE = 0)

        487
      • TABLE 29-14: Example SPI Mode Requirements (Master Mode, CKE = 0 or 1)

        488
      • FIGURE 29-12: Example SPI Master Mode Timing (CKE = 1)

        488
      • FIGURE 29-13: Example SPI Slave Mode Timing (CKE = 0)

        489
      • TABLE 29-15: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0 or 1)

        489
      • FIGURE 29-14: Example SPI Slave Mode Timing (CKE = 1)

        490
      • FIGURE 29-15: I2C™ Bus Start/Stop Bits Timing

        490
      • TABLE 29-16: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        491
      • FIGURE 29-16: I2C™ Bus Data Timing

        491
      • TABLE 29-17: I2C™ Bus Data Requirements (Slave Mode)

        492
      • FIGURE 29-17: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms

        493
      • TABLE 29-18: Master SSP I2C™ Bus Start/Stop Bits Requirements

        493
      • FIGURE 29-18: Master SSP I2C™ Bus Data Timing

        493
      • TABLE 29-19: Master SSP I2C™ Bus Data Requirements

        494
      • FIGURE 29-19: EUSART Synchronous Transmission (Master/Slave) Timing

        495
      • TABLE 29-20: EUSART Synchronous Transmission Requirements

        495
      • FIGURE 29-20: EUSART Synchronous Receive (Master/Slave) Timing

        495
      • TABLE 29-21: EUSART Synchronous Receive Requirements

        495
      • TABLE 29-22: A/D Converter Characteristics: PIC18(L)F2X/45K50

        496
      • FIGURE 29-21: A/D Conversion Timing

        496
      • TABLE 29-23: A/D Conversion Requirements (PIC18(L)F2X/45K50)

        497
• 30.0 DC and AC Characteristics Graphs and Charts

  499
• 31.0 Packaging Information

  501
  • 31.1 Package Marking Information

    501
  • 31.2 Package Details

    504
• Appendix A: Revision History

  519
  • Revision A (August 2012)

    519
• Appendix B: Device Differences

  520
  • TABLE B-1: Device Differences

    520
    • INDEX

      521
  • A

    521
  • B

    521
  • C

    522
  • D

    523
  • E

    523
  • F

    524
  • G

    524
  • H

    524
  • I

    524
  • L

    525
  • M

    525
  • N

    525
  • O

    525
  • P

    526
  • R

    526
  • S

    527
  • T

    527
  • U

    529
  • V

    529
  • W

    529
  • X

    529
  • Notes:

    530
    • The Microchip Web Site

      531
    • Customer Change Notification Service

      531
    • Customer Support

      531
    • Reader Response

      532
• Product Identification System

  533
  • Corporate Office

    536
  • Atlanta

    536
  • Boston

    536
  • Chicago

    536
  • Cleveland

    536
  • Fax: 216-447-0643

    536
  • Dallas

    536
  • Detroit

    536
  • Indianapolis

    536
  • Toronto

    536
  • Fax: 852-2401-3431

    536
  • Australia - Sydney

    536
  • China - Beijing

    536
  • China - Shanghai

    536
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    536
  • Korea - Daegu

    536
  • Korea - Seoul

    536
  • Singapore

    536
  • Taiwan - Taipei

    536
  • Fax: 43-7242-2244-393

    536
  • Denmark - Copenhagen

    536
  • France - Paris

    536
  • Germany - Munich

    536
  • Italy - Milan

    536
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    536
  • UK - Wokingham

    536
  • Worldwide Sales and Service

    536