Manuels d'utilisation pour Microchip Technology MA180025

Table des matières

• LCD Driver and Keypad Interface Features:

  3
• Low-Power Features:

  3
• Flexible Oscillator Structure:

  3
• Peripheral Highlights:

  3
• Special Microcontroller Features:

  3
• Special Microcontroller Features (Continued):

  4
• Pin Diagrams – PIC18F6XJ90

  5
• Pin Diagrams – PIC18F8XJ90

  6
• Table of Contents

  7
• Most Current Data Sheet

  8
• Errata

  8
• Customer Notification System

  8
• 1.0 Device Overview

  9
  • 1.1 Core Features

    9
    • 1.1.1 nanoWatt Technology

      9
    • 1.1.2 Oscillator Options and Features

      9
    • 1.1.3 Memory Options

      9
    • 1.1.4 Extended Instruction Set

      9
    • 1.1.5 Easy Migration

      9
  • 1.2 LCD Driver

    10
  • 1.3 Other Special Features

    10
  • 1.4 Details on Individual Family Members

    10
    • TABLE 1-1: Device Features for the PIC18F6XJ90 (64-pin Devices)

      11
    • TABLE 1-2: Device Features for the PIC18F8XJ90 (80-pin Devices)

      11
    • FIGURE 1-1: PIC18F6XJ90 (64-pin) Block Diagram

      12
    • FIGURE 1-2: PIC18F8XJ90 (80-pin) Block Diagram

      13
    • TABLE 1-3: PIC18F6XJ90 Pinout I/O Descriptions

      14
    • TABLE 1-4: PIC18F8XJ90 Pinout I/O Descriptions

      21
• 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers

  31
  • 2.1 Basic Connection Requirements

    31
    • FIGURE 2-1: Recommended Minimum connections

      31
  • 2.2 Power Supply Pins

    32
  • 2.3 Master Clear (MCLR) Pin

    32
    • FIGURE 2-2: Example of MCLR Pin Connections

      32
  • 2.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)

    33
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      33
  • 2.5 ICSP Pins

    33
  • 2.6 External Oscillator Pins

    34
  • 2.7 Unused I/Os

    34
    • FIGURE 2-4: Suggested Placement of the Oscillator Circuit

      34
• 3.0 Oscillator Configurations

  35
  • 3.1 Oscillator Types

    35
    • FIGURE 3-1: PIC18F87J90 Family Clock Diagram

      35
  • 3.2 Control Registers

    36
    • Register 3-1: OSCCON: Oscillator Control Register

      36
    • Register 3-2: OSCTUNE: Oscillator Tuning Register

      37
  • 3.3 Clock Sources and Oscillator Switching

    37
    • 3.3.1 Clock Source Selection

      38
    • 3.3.2 Oscillator Transitions

      38
  • 3.4 External Oscillator Modes

    39
    • 3.4.1 Crystal Oscillator/Ceramic Resonators (HS Modes)

      39
      • TABLE 3-1: Capacitor Selection for Ceramic Resonators

        39
      • TABLE 3-2: Capacitor Selection for Crystal Oscillator

        39
      • FIGURE 3-2: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)

        39
    • 3.4.2 External Clock Input (EC Modes)

      40
      • FIGURE 3-3: External Clock Input Operation (EC Configuration)

        40
      • FIGURE 3-4: External Clock Input Operation (HS OSC Configuration)

        40
    • 3.4.3 PLL Frequency Multiplier

      40
      • FIGURE 3-5: PLL Block Diagram

        40
  • 3.5 Internal Oscillator Block

    41
    • 3.5.1 INTIO Modes

      41
      • FIGURE 3-6: INTIO1 Oscillator Mode

        41
      • FIGURE 3-7: INTIO2 Oscillator Mode

        41
    • 3.5.2 INTPLL Modes

      41
    • 3.5.3 Internal Oscillator Output Frequency and Tuning

      42
    • 3.5.4 INTOSC Frequency Drift

      42
  • 3.6 Effects of Power-Managed Modes on the Various Clock Sources

    43
  • 3.7 Power-up Delays

    43
    • TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode

      43
• 4.0 Power-Managed Modes

  45
  • 4.1 Selecting Power-Managed Modes

    45
    • 4.1.1 Clock Sources

      45
    • 4.1.2 Entering Power-Managed Modes

      45
      • TABLE 4-1: Power-Managed Modes

        45
    • 4.1.3 Clock Transitions and Status Indicators

      46
    • 4.1.4 Multiple Sleep Commands

      46
  • 4.2 Run Modes

    46
    • 4.2.1 PRI_RUN Mode

      46
    • 4.2.2 SEC_RUN Mode

      46
      • FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode

        47
      • FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)

        47
    • 4.2.3 RC_RUN Mode

      48
      • FIGURE 4-3: Transition Timing to RC_RUN Mode

        48
      • FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode

        48
  • 4.3 Sleep Mode

    49
  • 4.4 Idle Modes

    49
    • FIGURE 4-5: Transition Timing for Entry to Sleep Mode

      49
    • FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)

      49
    • 4.4.1 PRI_IDLE Mode

      50
    • 4.4.2 SEC_IDLE Mode

      50
      • FIGURE 4-7: Transition Timing for Entry to Idle Mode

        50
      • FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode

        50
    • 4.4.3 RC_IDLE Mode

      51
  • 4.5 Exiting Idle and Sleep Modes

    51
    • 4.5.1 Exit By Interrupt

      51
    • 4.5.2 Exit By WDT Time-out

      51
    • 4.5.3 Exit By Reset

      51
    • 4.5.4 Exit Without an Oscillator Start-up Delay

      51
• 5.0 Reset

  53
  • 5.1 RCON Register

    53
    • FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit

      53
    • Register 5-1: RCON: Reset Control Register

      54
  • 5.2 Master Clear (MCLR)

    55
  • 5.3 Power-on Reset (POR)

    55
  • 5.4 Brown-out Reset (BOR)

    55
    • FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)

      55
    • 5.4.1 Detecting BOR

      55
  • 5.5 Configuration Mismatch (CM)

    55
  • 5.6 Power-up Timer (PWRT)

    56
    • 5.6.1 Time-out Sequence

      56
      • FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)

        56
      • FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1

        56
      • FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2

        57
      • FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)

        57
  • 5.7 Reset State of Registers

    58
    • TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register

      58
    • TABLE 5-2: Initialization Conditions for All Registers

      59
• 6.0 Memory Organization

  65
  • 6.1 Program Memory Organization

    65
    • FIGURE 6-1: Memory Maps for PIC18F87J90 Family Devices

      65
    • 6.1.1 Hard Memory Vectors

      66
      • FIGURE 6-2: Hard Vector and Configuration Word Locations for PIC18F87J90 Family Family Devices

        66
    • 6.1.2 Flash Configuration Words

      66
      • TABLE 6-1: Flash Configuration Word for PIC18F87J90 Family Devices

        66
    • 6.1.3 Program Counter

      67
    • 6.1.4 Return Address Stack

      67
      • FIGURE 6-3: Return Address Stack and Associated Registers

        67
      • Register 6-1: STKPTR: Stack Pointer Register

        68
    • 6.1.5 Fast Register Stack

      69
      • EXAMPLE 6-1: Fast Register Stack Code Example

        69
    • 6.1.6 Look-up Tables in Program Memory

      69
      • EXAMPLE 6-2: Computed GOTO Using an Offset Value

        69
  • 6.2 PIC18 Instruction Cycle

    70
    • 6.2.1 Clocking Scheme

      70
    • 6.2.2 Instruction Flow/Pipelining

      70
      • FIGURE 6-4: Clock/ Instruction Cycle

        70
      • EXAMPLE 6-3: Instruction Pipeline Flow

        70
    • 6.2.3 Instructions in Program Memory

      71
      • FIGURE 6-5: Instructions in Program Memory

        71
    • 6.2.4 Two-Word Instructions

      71
      • EXAMPLE 6-4: Two-Word Instructions

        71
  • 6.3 Data Memory Organization

    72
    • 6.3.1 Bank Select Register

      72
      • FIGURE 6-6: Data Memory Map for PIC18FX6J90 and PIC18FX7J90 Devices

        73
      • FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)

        74
    • 6.3.2 Access Bank

      74
    • 6.3.3 General Purpose Register File

      74
    • 6.3.4 Special Function Registers

      75
      • TABLE 6-2: Special Function Register Map for PIC18F87J90 Family Devices

        75
      • TABLE 6-3: PIC18F87J90 Family Register File Summary

        76
    • 6.3.5 STATUS Register

      81
      • Register 6-2: Status Register

        81
  • 6.4 Data Addressing Modes

    82
    • 6.4.1 Inherent and Literal Addressing

      82
    • 6.4.2 Direct Addressing

      82
    • 6.4.3 Indirect Addressing

      82
      • EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing

        82
      • FIGURE 6-8: Indirect Addressing

        83
  • 6.5 Program Memory and the Extended Instruction Set

    84
  • 6.6 Data Memory and the Extended Instruction Set

    85
    • 6.6.1 Indexed Addressing with Literal Offset

      85
    • 6.6.2 Instructions Affected By Indexed Literal Offset Mode

      85
      • FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)

        86
    • 6.6.3 Mapping the Access Bank in Indexed Literal Offset Mode

      87
    • 6.6.4 BSR in Indexed Literal Offset Mode

      87
      • FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing

        87
• 7.0 Flash Program Memory

  89
  • 7.1 Table Reads and Table Writes

    89
    • FIGURE 7-1: TABLE READ Operation

      89
    • FIGURE 7-2: Table Write Operation

      90
  • 7.2 Control Registers

    90
    • 7.2.1 EECON1 and EECON2 Registers

      90
      • Register 7-1: EECON1: EEPROM Control Register 1

        91
    • 7.2.2 Table Latch Register (TABLAT)

      92
    • 7.2.3 Table Pointer Register (TBLPTR)

      92
    • 7.2.4 Table Pointer Boundaries

      92
      • TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        92
      • FIGURE 7-3: Table Pointer Boundaries Based on Operation

        92
  • 7.3 Reading the Flash Program Memory

    93
    • FIGURE 7-4: Reads from Flash Program Memory

      93
    • EXAMPLE 7-1: Reading a Flash Program Memory Word

      93
  • 7.4 Erasing Flash Program Memory

    94
    • 7.4.1 Flash Program Memory Erase Sequence

      94
      • EXAMPLE 7-2: Erasing Flash Program Memory

        94
  • 7.5 Writing to Flash Program Memory

    95
    • FIGURE 7-5: Table Writes to Flash Program Memory

      95
    • 7.5.1 Flash Program Memory Write Sequence

      95
      • EXAMPLE 7-3: Writing to Flash Program Memory

        96
    • 7.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING).

      97
      • EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY

        97
    • 7.5.3 Write Verify

      98
    • 7.5.4 Unexpected Termination of Write Operation

      98
  • 7.6 Flash Program Operation During Code Protection

    98
    • TABLE 7-2: Registers Associated with Program Flash Memory

      98
• 8.0 8 X 8 Hardware Multiplier

  99
  • 8.1 Introduction

    99
  • 8.2 Operation

    99
    • EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine

      99
    • EXAMPLE 8-2: 8 x 8 Signed Multiply Routine

      99
    • TABLE 8-1: Performance Comparison for Various Multiply Operations

      99
    • EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm

      100
    • EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine

      100
    • EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm

      100
    • EXAMPLE 8-4: 16 x 16 Signed Multiply Routine

      100
• 9.0 Interrupts

  101
  • FIGURE 9-1: PIC18F87J90 Family Interrupt Logic

    102
  • 9.1 INTCON Registers

    103
    • Register 9-1: INTCON: Interrupt Control Register

      103
    • Register 9-2: INTCON2: Interrupt Control Register 2

      104
    • Register 9-3: INTCON3: Interrupt Control Register 3

      105
  • 9.2 PIR Registers

    106
    • Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1

      106
    • Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2

      107
    • Register 9-6: PIR3: Peripheral Interrupt Request (Flag) Register 3

      108
  • 9.3 PIE Registers

    109
    • Register 9-7: PIE1: Peripheral Interrupt Enable Register 1

      109
    • Register 9-8: PIE2: Peripheral Interrupt Enable Register 2

      110
    • Register 9-9: PIE3: Peripheral Interrupt Enable Register 3

      111
  • 9.4 IPR Registers

    112
    • Register 9-10: IPR1: Peripheral Interrupt Priority Register 1

      112
    • Register 9-11: IPR2: Peripheral Interrupt Priority Register 2

      113
    • Register 9-12: IPR3: Peripheral Interrupt Priority Register 3

      114
  • 9.5 RCON Register

    115
    • Register 9-13: RCON: Reset Control Register

      115
  • 9.6 INTx Pin Interrupts

    116
  • 9.7 TMR0 Interrupt

    116
  • 9.8 PORTB Interrupt-on-Change

    116
  • 9.9 Context Saving During Interrupts

    116
    • EXAMPLE 9-1: Saving STATUS, WREG and BSR Registers in RAM

      116
• 10.0 I/O Ports

  117
  • FIGURE 10-1: Generic I/O Port Operation

    117
  • 10.1 I/O Port Pin Capabilities

    117
    • 10.1.1 Input Pins and Voltage Considerations

      117
      • TABLE 10-1: Input Voltage Tolerance

        117
    • 10.1.2 Pin Output Drive

      117
      • TABLE 10-2: Output Drive Levels for Various ports

        118
    • 10.1.3 Pull-up Configuration

      118
    • 10.1.4 Open-Drain OUTPUTs

      118
      • FIGURE 10-2: Using the Open-Drain Output (USART Shown as Example)

        118
  • 10.2 PORTA, TRISA and LATA Registers

    118
    • EXAMPLE 10-1: Initializing PORTA

      118
    • TABLE 10-3: PORTA Functions

      119
    • TABLE 10-4: Summary of Registers Associated with PORTA

      119
  • 10.3 PORTB, TRISB and LATB Registers

    120
    • EXAMPLE 10-2: Initializing PORTB

      120
    • TABLE 10-5: PORTB Functions

      121
    • TABLE 10-6: Summary of Registers Associated with PORTB

      122
  • 10.4 PORTC, TRISC and LATC Registers

    123
    • EXAMPLE 10-3: Initializing PORTC

      123
    • TABLE 10-7: PORTC Functions

      124
    • TABLE 10-8: Summary of Registers Associated with PORTC

      125
  • 10.5 PORTD, TRISD and LATD Registers

    126
    • EXAMPLE 10-4: Initializing PORTD

      126
    • TABLE 10-9: PORTD Functions

      127
    • TABLE 10-10: Summary of Registers Associated with PORTD

      127
  • 10.6 PORTE, TRISE and LATE Registers

    128
    • TABLE 10-11: PORTE Pins Available in Different LCD Drive Configurations

      128
    • EXAMPLE 10-5: Initializing PORTE

      128
    • TABLE 10-12: PORTE Functions

      129
    • TABLE 10-13: Summary of Registers Associated with PORTE

      129
  • 10.7 PORTF, LATF and TRISF Registers

    130
    • EXAMPLE 10-6: Initializing PORTF

      130
    • TABLE 10-14: PORTF Functions

      131
    • TABLE 10-15: Summary of Registers Associated with PORTF

      132
  • 10.8 PORTG, TRISG and LATG Registers

    133
    • EXAMPLE 10-7: Initializing PORTG

      133
    • TABLE 10-16: PORTG Functions

      134
    • TABLE 10-17: Summary of Registers Associated with PORTG

      134
  • 10.9 PORTH, LATH and TRISH Registers

    135
    • EXAMPLE 10-8: Initializing PORTH

      135
    • TABLE 10-18: PORTH Functions

      136
    • TABLE 10-19: Summary of Registers Associated with PORTH

      136
  • 10.10 PORTJ, TRISJ and LATJ Registers

    137
    • EXAMPLE 10-9: Initializing PORTJ

      137
    • TABLE 10-20: PORTJ Functions

      138
    • TABLE 10-21: Summary of Registers Associated with PORTJ

      138
• 11.0 Timer0 Module

  139
  • Register 11-1: T0CON: Timer0 Control Register

    139
  • 11.1 Timer0 Operation

    140
  • 11.2 Timer0 Reads and Writes in 16-Bit Mode

    140
    • FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)

      140
    • FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)

      140
  • 11.3 Prescaler

    141
    • 11.3.1 Switching Prescaler Assignment

      141
  • 11.4 Timer0 Interrupt

    141
    • TABLE 11-1: Registers Associated with Timer0

      141
• 12.0 Timer1 Module

  143
  • Register 12-1: T1CON: Timer1 Control Register

    143
  • 12.1 Timer1 Operation

    144
    • FIGURE 12-1: Timer1 Block Diagram (8-Bit Mode)

      144
    • FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)

      144
  • 12.2 Timer1 16-Bit Read/Write Mode

    145
  • 12.3 Timer1 Oscillator

    145
    • FIGURE 12-3: External Components for the Timer1 LP Oscillator

      145
    • TABLE 12-1: Capacitor Selection for the Timer1 Oscillator(2,3,4)

      145
    • 12.3.1 Using Timer1 as a Clock Source

      145
    • 12.3.2 Timer1 Oscillator Layout Considerations

      146
      • FIGURE 12-4: Oscillator Circuit with Grounded Guard Ring

        146
  • 12.4 Timer1 Interrupt

    146
  • 12.5 Resetting Timer1 Using the CCP Special Event Trigger

    146
  • 12.6 Using Timer1 as a Real-Time Clock

    146
    • EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service

      147
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter

      147
• 13.0 Timer2 Module

  149
  • 13.1 Timer2 Operation

    149
    • Register 13-1: T2CON: Timer2 Control Register

      149
  • 13.2 Timer2 Interrupt

    150
  • 13.3 Timer2 Output

    150
    • FIGURE 13-1: Timer2 Block Diagram

      150
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter

      150
• 14.0 Timer3 Module

  151
  • Register 14-1: T3CON: Timer3 Control Register

    151
  • 14.1 Timer3 Operation

    152
    • FIGURE 14-1: Timer3 Block Diagram (8-Bit Mode)

      152
    • FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)

      152
  • 14.2 Timer3 16-Bit Read/Write Mode

    153
  • 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source

    153
  • 14.4 Timer3 Interrupt

    153
  • 14.5 Resetting Timer3 Using the CCP Special Event Trigger

    153
    • TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter

      153
• 15.0 Real-Time Clock and Calendar (RTCC)

  155
  • FIGURE 15-1: RTCC Block Diagram

    155
  • 15.1 RTCC Module Registers

    156
  • RTCC Control Registers

    156
  • RTCC Value Registers

    156
  • Alarm Value Registers

    156
    • 15.1.1 RTCC Control Registers

      157
      • Register 15-1: RTCCFG: RTCC Configuration Register(1)

        157
      • Register 15-2: RTCCAL: RTCC Calibration Register

        158
      • Register 15-3: PADCFG1: Pad Configuration Register

        158
      • Register 15-4: ALRMCFG: Alarm Configuration Register

        159
      • Register 15-5: ALRMRPT: Alarm Repeat Register

        160
    • 15.1.2 RTCVALH and RTCVALL Register Mappings

      160
      • Register 15-6: Reserved Register

        160
      • Register 15-7: Year: Year Value Register(1)

        160
      • Register 15-8: MontH: Month Value Register(1)

        161
      • Register 15-9: Day: Day Value Register(1)

        161
      • Register 15-10: Weekday: Weekday Value Register(1)

        161
      • Register 15-11: Hour: Hour Value Register(1)

        162
      • Register 15-12: MINUTE: Minute Value Register

        162
      • Register 15-13: SECOND: Second Value Register

        162
    • 15.1.3 ALRMVALH and ALRMVALL Register Mappings

      163
      • Register 15-14: ALRMMNTH: Alarm Month Value Register(1)

        163
      • Register 15-15: ALRMDAY: Alarm Day Value Register(1)

        163
      • Register 15-16: ALRMWd: Alarm Weekday Value Register(1)

        163
      • Register 15-17: ALRMHr: Alarm Hours Value Register(1)

        164
      • Register 15-18: ALRMMIN: Alarm Minutes Value Register

        164
      • Register 15-19: ALRMSEC: Alarm Seconds Value Register

        164
    • 15.1.4 RTCEN Bit Write

      165
  • 15.2 Operation

    165
    • 15.2.1 Register Interface

      165
      • FIGURE 15-2: Timer Digit Format

        165
      • FIGURE 15-3: Alarm Digit Format

        165
    • 15.2.2 Clock Source

      166
      • FIGURE 15-4: Clock Source Multiplexing

        166
    • 15.2.3 Digit Carry Rules

      166
      • TABLE 15-1: Day of Week Schedule

        166
      • TABLE 15-2: Day to Month Rollover Schedule

        166
    • 15.2.4 Leap Year

      167
    • 15.2.5 General Functionality

      167
    • 15.2.6 Safety Window for Register Reads and Writes

      167
    • 15.2.7 Write Lock

      167
      • EXAMPLE 15-1: Setting the RTCWREN Bit

        167
    • 15.2.8 Register Mapping

      167
      • TABLE 15-3: RTCVALH and RTCVALL Register Mapping

        167
      • TABLE 15-4: ALRMVAL Register Mapping

        168
    • 15.2.9 Calibration

      168
      • EQUATION 15-1: Converting Error, Clock Pulses

        168
  • 15.3 Alarm

    168
    • 15.3.1 Configuring the Alarm

      168
      • FIGURE 15-5: Alarm Mask Settings

        169
    • 15.3.2 Alarm Interrupt

      169
      • FIGURE 15-6: Timer Pulse Generation

        170
  • 15.4 Sleep Mode

    170
  • 15.5 Reset

    170
    • 15.5.1 Device Reset

      170
    • 15.5.2 Power-on Reset (POR)

      170
  • 15.6 Register Maps

    171
    • TABLE 15-5: RTCC Control Registers

      171
    • TABLE 15-6: RTCC Value Registers

      171
    • TABLE 15-7: Alarm Value Registers

      171
• 16.0 Capture/Compare/PWM (CCP) Modules

  173
  • Register 16-1: CCPxCON: CCPx Control Register (CCP1, CCP2 Modules)

    173
  • 16.1 CCP Module Configuration

    174
    • 16.1.1 CCP Modules and Timer Resources

      174
      • TABLE 16-1: CCP Mode – Timer Resource

        174
    • 16.1.2 Open-Drain Output Option

      174
    • 16.1.3 CCP2 Pin Assignment

      174
      • FIGURE 16-1: CCP and Timer Interconnect Configurations

        174
      • TABLE 16-2: Interactions Between CCP1 and CCP2 for Timer Resources

        175
  • 16.2 Capture Mode

    176
    • 16.2.1 CCP Pin Configuration

      176
    • 16.2.2 Timer1/Timer3 Mode Selection

      176
    • 16.2.3 Software Interrupt

      176
    • 16.2.4 CCP Prescaler

      176
      • EXAMPLE 16-1: Changing Between Capture Prescalers

        176
      • FIGURE 16-2: Capture Mode Operation Block Diagram

        176
  • 16.3 Compare Mode

    177
    • 16.3.1 CCP Pin Configuration

      177
    • 16.3.2 Timer1/Timer3 Mode Selection

      177
    • 16.3.3 Software Interrupt Mode

      177
    • 16.3.4 Special Event Trigger

      177
      • FIGURE 16-3: Compare Mode Operation Block Diagram

        177
      • TABLE 16-3: Registers Associated with Capture, Compare, Timer1 and Timer3

        178
  • 16.4 PWM Mode

    179
    • FIGURE 16-4: Simplified PWM Block Diagram

      179
    • FIGURE 16-5: PWM Output

      179
    • 16.4.1 PWM Period

      179
      • EQUATION 16-1:

        179
    • 16.4.2 PWM Duty Cycle

      180
      • EQUATION 16-2:

        180
      • EQUATION 16-3:

        180
      • TABLE 16-4: Example PWM Frequencies and Resolutions at 40 MHz

        180
    • 16.4.3 Setup for PWM Operation

      181
      • TABLE 16-5: Registers Associated with PWM and Timer2

        181
• 17.0 Liquid Crystal Display (LCD) Driver Module

  183
  • FIGURE 17-1: LCD Driver Module Block Diagram

    183
  • 17.1 LCD Registers

    184
    • 17.1.1 LCD Control Registers

      184
      • Register 17-1: LCDCON: LCD Control Register

        184
      • Register 17-2: LCDPS: LCD Phase Register

        185
      • Register 17-3: LCDSEx: LCD Segment Enable Registers

        186
      • TABLE 17-1: LCDSE Registers and Associated Segments

        186
    • 17.1.2 LCD Data Registers

      187
      • Register 17-4: LCDDATAx: LCD Data Registers

        187
      • TABLE 17-2: LCDDATA Registers and Bits for Segment and COM Combinations

        187
  • 17.2 LCD Clock Source

    188
    • 17.2.1 LCD Voltage Regulator Clock Source

      188
    • 17.2.2 Clock sOURCE cONSIDERATIONS

      188
      • FIGURE 17-2: LCD Clock Generation

        188
  • 17.3 LCD Bias Generation

    189
    • 17.3.1 LCD Bias Types

      189
    • 17.3.2 LCD Voltage Regulator

      189
      • Register 17-5: LCDREG: Voltage Regulator Control Register

        189
    • 17.3.3 Bias Configurations

      190
      • FIGURE 17-3: LCD Regulator connections for M0 and M1 Configurations

        190
      • FIGURE 17-4: Resistor ladder Connections for M2 configuration

        191
      • FIGURE 17-5: Resistor ladder Connections for M3 configuration

        192
    • 17.3.4 Design Considerations for The LCD Charge Pump

      193
      • EQUATION 17-1:

        193
  • 17.4 LCD Multiplex Types

    193
    • TABLE 17-3: PORTE<6:4> Function

      193
  • 17.5 Segment Enables

    193
  • 17.6 Pixel Control

    193
  • 17.7 LCD Frame Frequency

    194
    • TABLE 17-4: Frame Frequency Formulas

      194
    • TABLE 17-5: Approximate Frame Frequency (in Hz) for LP Prescaler Settings

      194
  • 17.8 LCD Waveform Generation

    194
    • FIGURE 17-6: Type-A/Type-B Waveforms in Static Drive

      195
    • FIGURE 17-7: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive

      196
    • FIGURE 17-8: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive

      197
    • FIGURE 17-9: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive

      198
    • FIGURE 17-10: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive

      199
    • FIGURE 17-11: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive

      200
    • FIGURE 17-12: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive

      201
    • FIGURE 17-13: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive

      202
    • FIGURE 17-14: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive

      203
    • FIGURE 17-15: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive

      204
    • FIGURE 17-16: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive

      205
  • 17.9 LCD Interrupts

    206
    • FIGURE 17-17: Example Waveforms and Interrupt Timing in Quarter Duty Cycle Drive

      206
  • 17.10 Operation During Sleep

    207
    • 17.10.1 Using the LCD Regulator During Sleep

      207
      • FIGURE 17-18: Sleep Entry/Exit When SLPEN = 1 or CS<1:0> = 00

        207
  • 17.11 Configuring the LCD Module

    208
    • TABLE 17-6: Registers Associated with LCD Operation

      209
• 18.0 Master Synchronous Serial Port (MSSP) Module

  211
  • 18.1 Master SSP (MSSP) Module Overview

    211
  • 18.2 Control Registers

    211
  • 18.3 SPI Mode

    211
    • FIGURE 18-1: MSSP Block Diagram (SPI Mode)

      211
    • 18.3.1 Registers

      212
      • Register 18-1: SSPSTAT: MSSP Status Register (SPI Mode)

        212
      • Register 18-2: SSPCON1: MSSP Control Register 1 (SPI Mode)

        213
    • 18.3.2 Operation

      214
      • EXAMPLE 18-1: Loading the SSPBUF (SSPSR) Register

        214
    • 18.3.3 Enabling SPI I/O

      215
    • 18.3.4 Open-Drain Output Option

      215
    • 18.3.5 Typical Connection

      215
      • FIGURE 18-2: SPI Master/Slave Connection

        215
    • 18.3.6 Master Mode

      216
      • FIGURE 18-3: SPI Mode Waveform (Master Mode)

        216
    • 18.3.7 Slave Mode

      217
    • 18.3.8 Slave Select Synchronization

      217
      • FIGURE 18-4: Slave Synchronization Waveform

        217
      • FIGURE 18-5: SPI Mode Waveform (Slave Mode with CKE = 0)

        218
      • FIGURE 18-6: SPI Mode Waveform (Slave Mode with CKE = 1)

        218
    • 18.3.9 Operation in Power-Managed Modes

      219
    • 18.3.10 Effects of a Reset

      219
    • 18.3.11 Bus Mode Compatibility

      219
      • TABLE 18-1: SPI Bus Modes

        219
      • TABLE 18-2: Registers Associated with SPI Operation

        219
  • 18.4 I2C Mode

    220
    • FIGURE 18-7: MSSP Block Diagram (I2C™ Mode)

      220
    • 18.4.1 Registers

      220
      • Register 18-3: SSPSTAT: MSSP Status Register (I2C™ Mode)

        221
      • Register 18-4: SSPCON1: MSSP Control Register 1 (I2C™ Mode)

        222
      • Register 18-5: SSPCON2: MSSP Control Register 2 (I2C™ Master Mode)

        223
      • Register 18-6: SSPCON2: MSSP Control Register 2 (I2C™ Slave Mode)

        224
    • 18.4.2 Operation

      225
    • 18.4.3 Slave Mode

      225
      • EXAMPLE 18-2: Address Masking Examples

        226
      • FIGURE 18-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Addressing)

        228
      • FIGURE 18-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)

        229
      • FIGURE 18-10: I2C™ Slave Mode Timing (Transmission, 7-bit Addressing)

        230
      • FIGURE 18-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Addressing)

        231
      • FIGURE 18-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Addressing)

        232
      • FIGURE 18-13: I2C™ Slave Mode Timing (Transmission, 10-bit Addressing)

        233
    • 18.4.4 Clock Stretching

      234
      • FIGURE 18-14: Clock Synchronization Timing

        235
      • FIGURE 18-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Addressing)

        236
      • FIGURE 18-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Addressing)

        237
    • 18.4.5 General Call Address Support

      238
      • FIGURE 18-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)

        238
    • 18.4.6 Master Mode

      239
      • FIGURE 18-18: MSSP Block Diagram (I2C™ Master Mode)

        239
    • 18.4.7 Baud Rate

      241
      • FIGURE 18-19: Baud Rate Generator Block Diagram

        241
      • TABLE 18-3: I2C™ Clock Rate w/BRG

        241
      • FIGURE 18-20: Baud Rate Generator Timing with Clock Arbitration

        242
    • 18.4.8 I2C Master Mode Start Condition Timing

      243
      • FIGURE 18-21: First Start Bit Timing

        243
    • 18.4.9 I2C Master Mode Repeated Start Condition Timing

      244
      • FIGURE 18-22: Repeated Start Condition Waveform

        244
    • 18.4.10 I2C Master Mode Transmission

      245
    • 18.4.11 I2C Master Mode Reception

      245
      • FIGURE 18-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Addressing)

        246
      • FIGURE 18-24: I2C™ Master Mode Waveform (Reception, 7-bit Addressing)

        247
    • 18.4.12 Acknowledge Sequence Timing

      248
    • 18.4.13 Stop Condition Timing

      248
      • FIGURE 18-25: Acknowledge Sequence Waveform

        248
      • FIGURE 18-26: Stop Condition Receive or Transmit Mode

        248
    • 18.4.14 Sleep Operation

      249
    • 18.4.15 Effects of a Reset

      249
    • 18.4.16 Multi-Master Mode

      249
    • 18.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration

      249
      • FIGURE 18-27: Bus Collision Timing for Transmit and Acknowledge

        249
      • FIGURE 18-28: Bus Collision During Start Condition (SDA Only)

        250
      • FIGURE 18-29: Bus Collision During Start Condition (SCL = 0)

        251
      • FIGURE 18-30: BRG Reset Due to SDA Arbitration During Start Condition

        251
      • FIGURE 18-31: Bus Collision During a Repeated Start Condition (Case 1)

        252
      • FIGURE 18-32: Bus Collision During Repeated Start Condition (Case 2)

        252
      • FIGURE 18-33: Bus Collision During a Stop Condition (Case 1)

        253
      • FIGURE 18-34: Bus Collision During a Stop Condition (Case 2)

        253
      • TABLE 18-4: Registers Associated with I2C™ Operation

        254
• 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  255
  • 19.1 Control Registers

    255
    • Register 19-1: TXSTA1: EUSART Transmit Status and Control Register

      256
    • Register 19-2: RCSTA1: EUSART Receive Status and Control Register

      257
    • Register 19-3: BAUDCON1: Baud Rate Control Register 1

      258
  • 19.2 EUSART Baud Rate Generator (BRG)

    259
    • 19.2.1 Operation in Power-Managed Modes

      259
    • 19.2.2 Sampling

      259
      • TABLE 19-1: Baud Rate Formulas

        259
      • EXAMPLE 19-1: Calculating Baud Rate Error

        259
      • TABLE 19-2: Registers Associated with the Baud Rate Generator

        259
      • TABLE 19-3: Baud Rates For Asynchronous Modes

        260
    • 19.2.3 Auto-Baud Rate Detect

      262
      • TABLE 19-4: BRG Counter Clock Rates

        262
      • FIGURE 19-1: Automatic Baud Rate Calculation

        263
      • FIGURE 19-2: BRG Overflow Sequence

        263
  • 19.3 EUSART Asynchronous Mode

    264
    • 19.3.1 EUSART Asynchronous Transmitter

      264
      • FIGURE 19-3: EUSART Transmit Block Diagram

        264
      • FIGURE 19-4: Asynchronous Transmission

        265
      • FIGURE 19-5: Asynchronous Transmission (Back to Back)

        265
      • TABLE 19-5: Registers Associated with Asynchronous Transmission

        265
    • 19.3.2 EUSART Asynchronous Receiver

      266
    • 19.3.3 Setting Up 9-bit Mode with Address Detect

      266
      • FIGURE 19-6: EUSART Receive Block Diagram

        266
      • FIGURE 19-7: Asynchronous Reception

        267
      • TABLE 19-6: Registers Associated with Asynchronous Reception

        267
    • 19.3.4 Auto-Wake-up On Sync Break Character

      268
      • FIGURE 19-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation

        268
      • FIGURE 19-9: Auto-Wake-up Bit (WUE) Timings During Sleep

        268
    • 19.3.5 Break Character Sequence

      269
    • 19.3.6 Receiving A Break Character

      269
      • FIGURE 19-10: Send Break Character Sequence

        269
  • 19.4 EUSART Synchronous Master Mode

    270
    • 19.4.1 EUSART Synchronous Master Transmission

      270
      • FIGURE 19-11: Synchronous Transmission

        270
      • FIGURE 19-12: Synchronous Transmission (Through TXEN)

        271
      • TABLE 19-7: Registers Associated with Synchronous Master Transmission

        271
    • 19.4.2 EUSART Synchronous Master Reception

      272
      • FIGURE 19-13: Synchronous Reception (Master Mode, SREN)

        272
      • TABLE 19-8: Registers Associated with Synchronous Master Reception

        272
  • 19.5 EUSART Synchronous Slave Mode

    273
    • 19.5.1 EUSART Synchronous Slave Transmit

      273
      • TABLE 19-9: Registers Associated with Synchronous Slave Transmission

        273
    • 19.5.2 EUSART Synchronous Slave Reception

      274
      • TABLE 19-10: Registers Associated with Synchronous Slave Reception

        274
• 20.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)

  275
  • 20.1 Control Registers

    275
    • Register 20-1: TXSTA2: AUSART Transmit Status and Control Register

      276
    • Register 20-2: RCSTA2: ausart Receive Status and Control Register

      277
  • 20.2 AUSART Baud Rate Generator (BRG)

    278
    • 20.2.1 Operation in Power-Managed Modes

      278
    • 20.2.2 Sampling

      278
      • TABLE 20-1: Baud Rate Formulas

        278
      • EXAMPLE 20-1: Calculating Baud Rate Error

        278
      • TABLE 20-2: Registers Associated with the Baud Rate Generator

        278
      • TABLE 20-3: Baud Rates for Asynchronous Modes

        279
  • 20.3 AUSART Asynchronous Mode

    280
    • 20.3.1 AUSART Asynchronous Transmitter

      280
      • FIGURE 20-1: AUSART Transmit Block Diagram

        280
      • FIGURE 20-2: Asynchronous Transmission

        281
      • FIGURE 20-3: Asynchronous Transmission (Back to Back)

        281
      • TABLE 20-4: Registers Associated with Asynchronous Transmission

        281
    • 20.3.2 AUSART Asynchronous Receiver

      282
    • 20.3.3 Setting Up 9-bit Mode with Address Detect

      282
      • FIGURE 20-4: AUSART Receive Block Diagram

        282
      • FIGURE 20-5: Asynchronous Reception

        283
      • TABLE 20-5: Registers Associated with Asynchronous Reception

        283
  • 20.4 AUSART Synchronous Master Mode

    284
    • 20.4.1 AUSART Synchronous Master Transmission

      284
      • FIGURE 20-6: Synchronous Transmission

        284
      • FIGURE 20-7: Synchronous Transmission (Through Txen)

        285
      • TABLE 20-6: Registers Associated with Synchronous Master Transmission

        285
    • 20.4.2 AUSART Synchronous Master Reception

      286
      • FIGURE 20-8: Synchronous Reception (Master Mode, SREN)

        286
      • TABLE 20-7: Registers Associated with Synchronous Master Reception

        286
  • 20.5 AUSART Synchronous Slave Mode

    287
    • 20.5.1 AUSART Synchronous Slave Transmit

      287
      • TABLE 20-8: Registers Associated with Synchronous Slave Transmission

        287
    • 20.5.2 AUSART Synchronous Slave Reception

      288
      • TABLE 20-9: Registers Associated with Synchronous Slave Reception

        288
• 21.0 10-Bit Analog-to-Digital Converter (A/D) Module

  289
  • Register 21-1: ADCON0: A/D Control Register 0

    289
  • Register 21-2: ADCON1: A/D Control Register 1

    290
  • Register 21-3: ADCON2: A/D Control Register 2

    291
  • FIGURE 21-1: A/D Block Diagram(1,2)

    292
  • FIGURE 21-2: Analog Input Model

    293
  • 21.1 A/D Acquisition Requirements

    294
    • EQUATION 21-1: A/D Acquisition Time

      294
    • EQUATION 21-2: A/D Minimum Charging Time

      294
    • EQUATION 21-3: Calculating the Minimum Required Acquisition Time

      294
  • 21.2 Selecting and Configuring Automatic Acquisition Time

    295
  • 21.3 Selecting the A/D Conversion Clock

    295
    • TABLE 21-1: Tad vs. Device Operating Frequencies

      295
  • 21.4 Configuring Analog Port Pins

    295
  • 21.5 A/D Conversions

    296
  • 21.6 Use of the CCP2 Trigger

    296
    • FIGURE 21-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)

      296
    • FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)

      296
  • 21.7 A/D Converter Calibration

    297
  • 21.8 Operation in Power-Managed Modes

    297
    • TABLE 21-2: Summary of A/D Registers

      297
• 22.0 Comparator Module

  299
  • Register 22-1: CMCON: Comparator Module Control Register

    299
  • 22.1 Comparator Configuration

    300
    • FIGURE 22-1: Comparator I/O Operating Modes

      300
  • 22.2 Comparator Operation

    301
  • 22.3 Comparator Reference

    301
    • FIGURE 22-2: Single Comparator

      301
    • 22.3.1 External Reference Signal

      301
    • 22.3.2 Internal Reference Signal

      301
  • 22.4 Comparator Response Time

    301
  • 22.5 Comparator Outputs

    301
    • FIGURE 22-3: Comparator Output Block Diagram

      302
  • 22.6 Comparator Interrupts

    302
  • 22.7 Comparator Operation During Sleep

    302
  • 22.8 Effects of a Reset

    302
  • 22.9 Analog Input Connection Considerations

    303
    • FIGURE 22-4: Comparator Analog Input Model

      303
    • TABLE 22-1: Registers Associated with Comparator Module

      303
• 23.0 Comparator Voltage Reference Module

  305
  • 23.1 Configuring the Comparator Voltage Reference

    305
    • Register 23-1: CVRCON: Comparator Voltage Reference Control Register

      305
    • FIGURE 23-1: Comparator Voltage Reference Block Diagram

      306
  • 23.2 Voltage Reference Accuracy/Error

    306
  • 23.3 Operation During Sleep

    306
  • 23.4 Effects of a Reset

    306
  • 23.5 Connection Considerations

    306
    • FIGURE 23-2: Comparator Voltage Reference Output Buffer Example

      307
    • TABLE 23-1: Registers Associated with Comparator Voltage Reference

      307
• 24.0 Charge Time Measurement Unit (CTMU)

  309
  • FIGURE 24-1: CTMU Block Diagram

    309
  • 24.1 CTMU Operation

    310
    • 24.1.1 Theory of Operation

      310
    • 24.1.2 Current Source

      310
    • 24.1.3 Edge Selection and Control

      310
    • 24.1.4 Edge Status

      310
    • 24.1.5 Interrupts

      311
  • 24.2 CTMU Module Initialization

    311
  • 24.3 Calibrating the CTMU Module

    311
    • 24.3.1 Current Source Calibration

      311
      • FIGURE 24-2: CTMU Current Source Calibration Circuit

        312
      • EXAMPLE 24-1: Setup for CTMU Calibration Routines

        313
      • EXAMPLE 24-2: Current Calibration Routine

        314
    • 24.3.2 Capacitance Calibration

      315
      • EXAMPLE 24-3: Capacitance Calibration Routine

        316
  • 24.4 Measuring Capacitance with the CTMU

    317
    • 24.4.1 Absolute Capacitance Measurement

      317
    • 24.4.2 Relative Charge Measurement

      317
      • EXAMPLE 24-4: Routine for Capacitive Touch Switch

        318
  • 24.5 Measuring Time with the CTMU Module

    319
    • FIGURE 24-3: Typical Connections and Internal Configuration for Time Measurement

      319
  • 24.6 Creating a Delay with the CTMU Module

    320
    • FIGURE 24-4: Typical Connections and Internal Configuration for Pulse Delay Generation

      320
  • 24.7 Operation During Sleep/Idle Modes

    320
    • 24.7.1 Sleep Mode and Deep Sleep Modes

      320
    • 24.7.2 Idle Mode

      320
  • 24.8 Effects of a Reset on CTMU

    320
  • 24.9 Registers

    321
    • Register 24-1: CTMUCONH: CTMU Control High Register

      321
    • Register 24-2: CTMUCONL: CTMU Control Low Register

      322
    • Register 24-3: CTMUICON: CTMU current Control Register

      323
    • TABLE 24-1: Registers Associated with CTMU Module

      323
• 25.0 Special Features of the CPU

  325
  • 25.1 Configuration Bits

    325
    • 25.1.1 Considerations for Configuring PIC18F87J90 Family Devices

      325
      • TABLE 25-1: Mapping of the Flash Configuration Words to the Configuration Registers

        325
      • TABLE 25-2: Configuration Bits and Device IDs

        326
      • Register 25-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)

        327
      • Register 25-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)

        327
      • Register 25-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)

        328
      • Register 25-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)

        329
      • Register 25-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)

        329
      • Register 25-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)

        330
      • Register 25-7: DEVID1: Device ID Register 1 for PIC18F87J90 Family Devices

        330
      • Register 25-8: DEVID2: Device ID Register 2 for PIC18F87J90 Family Devices

        330
  • 25.2 Watchdog Timer (WDT)

    331
    • 25.2.1 Control Register

      331
      • FIGURE 25-1: WDT Block Diagram

        331
      • Register 25-9: WDTCON: Watchdog Timer Control Register

        332
      • TABLE 25-3: Summary of Watchdog Timer Registers

        332
  • 25.3 On-Chip Voltage Regulator

    333
    • 25.3.1 VOLTAGE REGULATION AND LOW-VOLTAGE DETECTION

      333
      • FIGURE 25-2: Connections for the On-chip Regulator

        333
    • 25.3.2 On-Chip Regulator and BOR

      334
    • 25.3.3 Power-up Requirements

      334
    • 25.3.4 OPERATION IN SLEEP MODE

      334
  • 25.4 Two-Speed Start-up

    334
    • FIGURE 25-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)

      334
    • 25.4.1 Special Considerations for Using Two-Speed Start-up

      335
  • 25.5 Fail-Safe Clock Monitor

    335
    • FIGURE 25-4: FSCM Block Diagram

      335
    • 25.5.1 FSCM and the Watchdog Timer

      335
      • FIGURE 25-5: FSCM Timing Diagram

        336
    • 25.5.2 Exiting Fail-Safe Operation

      336
    • 25.5.3 FSCM Interrupts in Power-Managed Modes

      336
    • 25.5.4 POR or Wake-up From Sleep

      336
  • 25.6 Program Verification and Code Protection

    337
    • 25.6.1 Configuration Register Protection

      337
  • 25.7 In-Circuit Serial Programming

    337
  • 25.8 In-Circuit Debugger

    337
    • TABLE 25-4: Debugger Resources

      337
• 26.0 Instruction Set Summary

  339
  • 26.1 Standard Instruction Set

    339
    • TABLE 26-1: Opcode Field Descriptions

      340
    • FIGURE 26-1: General Format for Instructions

      341
    • TABLE 26-2: PIC18F87J90 Family Instruction Set

      342
    • 26.1.1 Standard Instruction Set

      345
  • 26.2 Extended Instruction Set

    381
    • 26.2.1 Extended Instruction Syntax

      381
      • TABLE 26-3: Extensions to the PIC18 Instruction Set

        381
    • 26.2.2 Extended Instruction Set

      382
    • 26.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode

      386
    • 26.2.4 Considerations When Enabling the Extended Instruction Set

      386
    • 26.2.5 Special Considerations with Microchip MPLAB® IDE Tools

      388
• 27.0 Development Support

  389
  • 27.1 MPLAB Integrated Development Environment Software

    389
  • 27.2 MPLAB C Compilers for Various Device Families

    390
  • 27.3 HI-TECH C for Various Device Families

    390
  • 27.4 MPASM Assembler

    390
  • 27.5 MPLINK Object Linker/ MPLIB Object Librarian

    390
  • 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    390
  • 27.7 MPLAB SIM Software Simulator

    391
  • 27.8 MPLAB REAL ICE In-Circuit Emulator System

    391
  • 27.9 MPLAB ICD 3 In-Circuit Debugger System

    391
  • 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    391
  • 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    392
  • 27.12 MPLAB PM3 Device Programmer

    392
  • 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    392
• 28.0 Electrical Characteristics

  393
  • Absolute Maximum Ratings(†)

    393
    • FIGURE 28-1: Voltage-frequency Graph, Regulator Enabled (Industrial)(1)

      394
    • FIGURE 28-2: Voltage-frequency Graph, Regulator Disabled (Industrial)(1,2)

      394
  • 28.1 DC Characteristics: Supply Voltage PIC18F87J90 Family (Industrial)

    395
  • 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J90 Family (Industrial)

    396
  • 28.3 DC Characteristics: PIC18F87J90 Family (Industrial)

    404
  • 28.4 DC Characteristics: CTMU Current Source Specifications

    405
    • TABLE 28-1: Memory Programming Requirements

      406
    • TABLE 28-2: Comparator Specifications

      407
    • TABLE 28-3: Voltage Reference Specifications

      407
    • TABLE 28-4: Internal Voltage Regulator Specifications

      407
    • TABLE 28-5: Internal LCD Voltage Regulator Specifications

      407
  • 28.5 AC (Timing) Characteristics

    408
    • 28.5.1 Timing Parameter Symbology

      408
    • 28.5.2 Timing Conditions

      409
      • TABLE 28-6: Temperature and Voltage Specifications – AC

        409
      • FIGURE 28-3: Load Conditions for Device Timing Specifications

        409
    • 28.5.3 Timing Diagrams and Specifications

      410
      • FIGURE 28-4: External Clock Timing

        410
      • TABLE 28-7: External Clock Timing Requirements

        410
      • TABLE 28-8: PLL Clock Timing Specifications (Vdd = 2.15V to 3.6V)

        411
      • TABLE 28-9: Internal RC Accuracy (INTOSC and INTRC Sources)

        411
      • FIGURE 28-5: CLKO and I/O Timing

        412
      • TABLE 28-10: CLKO and I/O Timing Requirements

        412
      • FIGURE 28-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        413
      • TABLE 28-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements

        413
      • FIGURE 28-7: Timer0 and Timer1 External Clock Timings

        414
      • TABLE 28-12: Timer0 and Timer1 External Clock Requirements

        414
      • FIGURE 28-8: Capture/Compare/PWM Timings (CCP1, CCP2 Modules)

        415
      • TABLE 28-13: Capture/Compare/PWM Requirements (CCP1, CCP2 Modules)

        415
      • FIGURE 28-9: Example SPI Master Mode Timing (CKE = 0)

        416
      • TABLE 28-14: Example SPI Mode Requirements (Master Mode, Cke = 0)

        416
      • FIGURE 28-10: Example SPI Master Mode Timing (CKE = 1)

        417
      • TABLE 28-15: Example SPI Mode Requirements (Master Mode, CKE = 1)

        417
      • FIGURE 28-11: Example SPI Slave Mode Timing (CKE = 0)

        418
      • TABLE 28-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)

        418
      • FIGURE 28-12: Example SPI Slave Mode Timing (CKE = 1)

        419
      • TABLE 28-17: Example SPI Slave Mode Requirements (CKE = 1)

        419
      • FIGURE 28-13: I2C™ Bus Start/Stop Bits Timing

        420
      • TABLE 28-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        420
      • FIGURE 28-14: I2C™ Bus Data Timing

        421
      • TABLE 28-19: I2C™ Bus Data Requirements (Slave Mode)

        421
      • FIGURE 28-15: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms

        422
      • TABLE 28-20: MSSP I2C™ Bus Start/Stop Bits Requirements

        422
      • FIGURE 28-16: MSSP I2C™ Bus Data Timing

        422
      • TABLE 28-21: MSSP I2C™ Bus Data Requirements

        423
      • FIGURE 28-17: EUSART/AUSART Synchronous Transmission (Master/Slave) Timing

        424
      • TABLE 28-22: EUSART/AUSART Synchronous Transmission Requirements

        424
      • FIGURE 28-18: EUSART/AUSART Synchronous Receive (Master/Slave) Timing

        424
      • TABLE 28-23: EUSART/AUSART Synchronous Receive Requirements

        424
      • TABLE 28-24: A/D Converter Characteristics: PIC18F87J90 Family (Industrial)

        425
      • FIGURE 28-19: A/D Conversion Timing

        426
      • TABLE 28-25: A/D Conversion Requirements

        426
• 29.0 Packaging Information

  427
  • 29.1 Package Marking Information

    427
  • 29.2 Package Details

    428
• Appendix A: Revision History

  433
  • Revision A (October 2008)

    433
  • Revision B (December 2008)

    433
  • Revision C (February 2009)

    433
  • Revision D (January 2010)

    433
• Appendix B: Migration From PIC18F85J90 to PIC18F87J90

  433
  • TABLE B-1: Notable Differences Between PIC18F87J90 and PIC18F85J90 Families

    433
• INDEX

  435
• The Microchip Web Site

  447
• Customer Change Notification Service

  447
• Customer Support

  447
• Reader Response

  448
• Product Identification System

  449
• Worldwide Sales and Service

  450