Manuels d'utilisation pour Microchip Technology MA330025-1

Table des matières

• Operating Conditions

  1
• Core: 16-Bit dsPIC33E/PIC24E CPU

  1
• Clock Management

  1
• Power Management

  1
• High-Speed PWM

  1
• Advanced Analog Features

  1
• Timers/Output Compare/Input Capture

  1
• Communication Interfaces

  1
• Direct Memory Access (DMA)

  1
• Input/Output

  1
• Qualification and Class B Support

  1
• Debugger Development Support

  1
• dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Product Families

  2
  • TABLE 1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Controller Families

    2
  • Pin Diagrams

    3
  • Pin Diagrams

    4
  • Pin Diagrams

    5
  • Pin Diagrams (Continued)

    6
  • Pin Diagrams (Continued)

    7
  • Pin Diagrams (Continued)

    8
  • Pin Diagrams (Continued)

    9
  • Pin Diagrams (Continued)

    10
  • Pin Diagrams (Continued)

    11
    • TABLE 2: Pin Names: dsPIC33EP256MU810 and dsPIC33EP512MU810 dEVICES(1,2)

      12
  • Pin Diagrams (Continued)

    14
    • TABLE 3: Pin Names: PIC24EP256GU810 AND PIC24EP512GU810 dEVICES(1,2)

      15
  • Pin Diagrams (Continued)

    17
  • Pin Diagrams (Continued)

    18
  • Table of Contents

    19
  • Most Current Data Sheet

    20
  • Errata

    20
  • Customer Notification System

    20
  • Referenced Sources

    21
• 1.0 Device Overview

  23
  • FIGURE 1-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Block Diagram

    24
  • TABLE 1-1: Pinout I/O Descriptions

    25
• 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers and Microcontrollers

  31
  • 2.1 Basic Connection Requirements

    31
  • 2.2 Decoupling Capacitors

    31
    • FIGURE 2-1: Recommended Minimum connection

      32
    • 2.2.1 Tank Capacitors

      32
  • 2.3 CPU Logic Filter Capacitor Connection (Vcap)

    32
  • 2.4 Master Clear (MCLR) Pin

    32
    • FIGURE 2-2: Example of MCLR Pin Connections

      32
  • 2.5 ICSP Pins

    33
  • 2.6 External Oscillator Pins

    33
    • FIGURE 2-3: Suggested Placement of the Oscillator Circuit

      33
  • 2.7 Oscillator Value Conditions on Device Start-up

    33
  • 2.8 Unused I/Os

    33
  • 2.9 Application Examples

    34
    • FIGURE 2-4: Boost Converter Implementation

      34
    • FIGURE 2-5: Single-Phase Synchronous Buck converter

      35
    • FIGURE 2-6: Multi-Phase Synchronous Buck converter

      35
    • FIGURE 2-7: Interleaved PFC

      36
    • FIGURE 2-8: BEMF voltage measured using the ADC Module

      36
• 3.0 CPU

  37
  • 3.1 Registers

    37
  • 3.2 Instruction Set

    37
  • 3.3 Data Space Addressing

    37
  • 3.4 Addressing Modes

    37
    • FIGURE 3-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 CPU Block Diagram

      38
  • 3.5 Programmer’s Model

    39
    • TABLE 3-1: Programmer’s Model Register Descriptions

      39
    • FIGURE 3-2: Programmer’s Model

      40
  • 3.6 CPU Resources

    41
    • 3.6.1 Key Resources

      41
  • 3.7 CPU Control Registers

    42
    • Register 3-1: SR: CPU Status Register

      42
    • Register 3-2: CORCON: Core Control Register

      44
  • 3.8 Arithmetic Logic Unit (ALU)

    46
    • 3.8.1 Multiplier

      46
    • 3.8.2 Divider

      46
  • 3.9 DSP Engine (dsPIC33EPXXX(GP/ MC/MU)806/810/814 Devices Only)

    46
    • TABLE 3-2: DSP Instructions Summary

      46
• 4.0 Memory Organization

  47
  • 4.1 Program Address Space

    47
    • FIGURE 4-1: Program Memory Map for dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Devices(1)

      47
    • 4.1.1 Program Memory Organization

      48
    • 4.1.2 Interrupt and Trap Vectors

      48
      • FIGURE 4-2: Program Memory Organization

        48
  • 4.2 Data Address Space

    49
    • 4.2.1 Data Space Width

      49
    • 4.2.2 Data Memory Organization and Alignment

      49
    • 4.2.3 SFR Space

      49
    • 4.2.4 Near Data Space

      49
      • FIGURE 4-3: Data Memory Map for dsPIC33EP512(GP/MC/MU)806/810/814 Devices with 52-Kbyte RAM

        50
      • FIGURE 4-4: Data Memory Map for PIC24EP512(GP/GU)806/810/814 Devices with 52-Kbyte RAM

        51
      • FIGURE 4-5: Data Memory Map for dsPIC33EP256MU806/810/814 Devices with 28-Kbyte RAM

        52
      • FIGURE 4-6: Data Memory Map for PIC24EP256GU810/814 Devices with 28-Kbyte RAM

        53
    • 4.2.5 X and Y Data Spaces

      54
    • 4.2.6 DMA RAM

      54
  • 4.3 Program Memory Resources

    54
    • 4.3.1 Key Resources

      54
  • 4.4 Special Function Register Maps

    54
    • TABLE 4-1: CPU Core Register Map for dsPIC33EPXXX(GP/MC/MU)806/810/814 Devices Only

      55
    • TABLE 4-2: CPU Core Register Map for PIC24EPXXX(GP/GU)810/814 Devices Only

      57
    • TABLE 4-3: Interrupt Controller Register Map for dsPIC33EPXXXMU814 Devices Only

      58
    • TABLE 4-4: Interrupt Controller Register Map for dsPIC33EPXXXMU810 Devices Only

      60
    • TABLE 4-5: Interrupt Controller Register Map for dsPIC33EPXXXMU806 Devices Only

      62
    • TABLE 4-6: Interrupt Controller Register Map for dsPIC33EPXXXMC806 Devices Only

      64
    • TABLE 4-7: Interrupt Controller Register Map for dsPIC33EPXXXGP806 and PIC24EPXXXGP806 Devices Only

      66
    • TABLE 4-8: Interrupt Controller Register Map for PIC24EPXXXGU810/814 Devices Only

      68
    • TABLE 4-9: Timer1 through Timer9 Register Map

      70
    • TABLE 4-10: Input Capture 1 through Input Capture 16 Register Map

      71
    • TABLE 4-11: Output Compare 1 through Output Compare 16 Register Map

      73
    • TABLE 4-12: PWM Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only

      76
    • TABLE 4-13: PWM Generator 1 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only

      76
    • TABLE 4-14: PWM Generator 2 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only

      77
    • TABLE 4-15: PWM Generator 3 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only

      77
    • TABLE 4-16: PWM Generator 4 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only

      78
    • TABLE 4-17: PWM Generator 5 Register Map for dsPIC33EPXXX(MC/MU)810/814 Devices Only

      78
    • TABLE 4-18: PWM Generator 6 Register Map for dsPIC33EPXXX(MC/MU)810/814 Devices Only

      79
    • TABLE 4-19: PWM Generator 7 Register Map for dsPIC33EPXXX(MC/MU)814 Devices Only

      79
    • TABLE 4-20: QEI1 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only

      80
    • TABLE 4-21: QEI2 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only

      81
    • TABLE 4-22: I2C1 and I2C2 Register Map

      82
    • TABLE 4-23: UART1, UART2, UART3 and UART4 Register Map

      83
    • TABLE 4-24: SPI1, SPI2, SPI3 and SPI4 Register Map

      84
    • TABLE 4-25: ADC1 and ADC2 Register Map

      85
    • TABLE 4-26: DCI Register Map

      87
    • TABLE 4-27: USB OTG Register Map for dsPIC33EPMU806/810/814 and PIC24EPGU806/10/814) Devices Only

      88
    • TABLE 4-28: ECAN1 Register Map When WIN (C1CTRL<0>) = 0 or 1

      90
    • TABLE 4-29: ECAN1 Register Map When WIN (C1CTRL<0>) = 0

      90
    • TABLE 4-30: ECAN1 Register Map When WIN (C1CTRL<0>) = 1

      91
    • TABLE 4-31: ECAN2 Register Map When WIN (C2CTRL<0>) = 0 or 1

      93
    • TABLE 4-32: ECAN2 Register Map When WIN (C2CTRL<0>) = 0

      93
    • TABLE 4-33: ECAN2 Register Map When WIN (C2CTRL<0>) = 1

      94
    • TABLE 4-34: Parallel Master/Slave Port Register Map

      96
    • TABLE 4-35: CRC Register Map

      96
    • TABLE 4-36: Real-Time Clock and Calendar Register Map

      96
    • TABLE 4-37: Peripheral Pin Select Output Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only

      97
    • TABLE 4-38: Peripheral Pin Select Output Register Map for dsPIC33EPXXXMU806 Devices Only

      98
    • TABLE 4-39: Peripheral Pin Select Output Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only

      98
    • TABLE 4-40: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMU814 Devices Only

      99
    • TABLE 4-41: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMU810 Devices Only

      101
    • TABLE 4-42: Peripheral Pin Select Input Register Map for dsPIC33EPXXX(MC/MU)806 Devices Only

      103
    • TABLE 4-43: Peripheral Pin Select Input Register Map for PIC24EPXXXGU810/814 Devices Only

      105
    • TABLE 4-44: Reference Clock Register Map

      106
    • TABLE 4-45: NVM Register Map

      106
    • TABLE 4-46: System Control Register Map

      106
    • TABLE 4-47: PMD Register Map for dsPIC33EPXXXMU814 Devices Only

      107
    • TABLE 4-48: PMD Register Map for dsPIC33EPXXXMU810 Devices Only

      107
    • TABLE 4-49: PMD Register Map for dsPIC33EPXXXMU806 Devices Only

      108
    • TABLE 4-50: PMD Register Map for dsPIC33EPXXXMC806 Devices Only

      108
    • TABLE 4-51: PMD Register Map for dsPIC33EPXXXGP8XX and PIC24EPXXXGP8XX Devices Only

      109
    • TABLE 4-52: PMD Register Map for PIC24EPXXXGU810/814 Devices Only

      109
    • TABLE 4-53: Comparator Register Map

      110
    • TABLE 4-54: DMAC Register Map

      111
    • TABLE 4-55: PORTA Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only

      115
    • TABLE 4-56: PORTB Register Map

      115
    • TABLE 4-57: PORTC Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only

      115
    • TABLE 4-58: PORTC Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only

      116
    • TABLE 4-59: PORTD Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only

      116
    • TABLE 4-60: PORTD Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only

      116
    • TABLE 4-61: PORTE Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only

      117
    • TABLE 4-62: PORTE Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only

      117
    • TABLE 4-63: PORTF Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only

      117
    • TABLE 4-64: PORTF Register Map for dsPIC33EPXXX(GP/MC)806 and PIC24EPXXXGP806 Devices Only

      118
    • TABLE 4-65: PORTF Register Map for dsPIC33EPXXXMU806 Devices Only

      118
    • TABLE 4-66: PORTG Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only

      118
    • TABLE 4-67: PORTG Register Map for dsPIC33EPXXX(GP/MC)806 and PIC24EPXXXGP806 Devices Only

      119
    • TABLE 4-68: PORTG Register Map for dsPIC33EPXXXMU806 Devices Only

      119
    • TABLE 4-69: PORTH Register Map for dsPIC33EPXXXMU814 and PIC24EPXXXGU814 Devices Only

      120
    • TABLE 4-70: PORTJ Register Map for dsPIC33EPXXXMU814 and PIC24EPXXXGU814 Devices Only

      120
    • TABLE 4-71: PORTK Register Map for dsPIC33EPXXXMU814 and PIC24EPXXXGU814 Devices Only

      121
    • TABLE 4-72: Pad Configuration Register Map

      121
    • 4.4.1 Paged Memory Scheme

      122
      • EXAMPLE 4-1: Extended Data Space (EDS) Read Address Generation

        122
      • EXAMPLE 4-2: Extended Data Space (EDS) Write Address Generation

        123
      • EXAMPLE 4-3: Paged Data Memory Space

        124
      • TABLE 4-73: Overflow and Underflow Scenarios at Page 0, EDS and PSV Space Boundaries(2,3,4)

        125
    • 4.4.2 Extended X Data Space

      126
      • FIGURE 4-7: EDS Memory Map

        126
    • 4.4.3 EDS Arbitration and Bus Master Priority

      127
      • TABLE 4-74: EDS Bus Arbiter Priority

        127
      • FIGURE 4-8: EDS Arbiter Architecture

        127
    • 4.4.4 Software Stack

      128
      • FIGURE 4-9: CALL Stack Frame

        128
  • 4.5 Instruction Addressing Modes

    128
    • 4.5.1 File Register Instructions

      128
    • 4.5.2 MCU Instructions

      128
      • TABLE 4-75: Fundamental Addressing Modes Supported

        129
    • 4.5.3 Move and Accumulator Instructions

      129
    • 4.5.4 MAC Instructions (dsPIC33EPXXXMU806/810/814 Devices Only)

      129
    • 4.5.5 Other Instructions

      129
  • 4.6 Modulo Addressing (dsPIC33EPXXXMU806/810/814 Devices Only)

    130
    • 4.6.1 Start and End Address

      130
    • 4.6.2 W Address Register Selection

      130
      • FIGURE 4-10: Modulo Addressing Operation Example

        130
    • 4.6.3 Modulo Addressing Applicability

      131
  • 4.7 Bit-Reversed Addressing (dsPIC33EPXXXMU806/810/814 Devices Only)

    131
    • 4.7.1 Bit-Reversed Addressing Implementation

      131
      • FIGURE 4-11: Bit-Reversed Address Example

        132
      • TABLE 4-76: Bit-Reversed Address Sequence (16-Entry)

        132
  • 4.8 Interfacing Program and Data Memory Spaces

    133
    • TABLE 4-77: Program Space Address Construction

      133
    • FIGURE 4-12: Data Access from Program Space Address Generation

      133
    • 4.8.1 Data Access From Program Memory Using Table Instructions

      134
      • FIGURE 4-13: Accessing Program Memory with Table Instructions

        134
• 5.0 Flash Program Memory

  135
  • 5.1 Table Instructions and Flash Programming

    135
    • FIGURE 5-1: Addressing for Table Registers

      135
  • 5.2 RTSP Operation

    136
  • 5.3 Programming Operations

    136
    • EQUATION 5-1: Programming Time

      136
    • EQUATION 5-2: Minimum Row Write Time

      136
    • EQUATION 5-3: Maximum Row Write Time

      136
  • 5.4 Flash Program Memory Resources

    137
    • 5.4.1 Key Resources

      137
  • 5.5 Control Registers

    137
    • Register 5-1: NVMCON: Non-Volatile Memory (NVM) Control Register

      138
    • Register 5-2: NVMADRU: NonVolatile Memory Upper Address Register

      139
    • Register 5-3: NVMADR: NonVolatile Memory Address Register

      139
    • Register 5-4: NVMKEY: NonVolatile Memory Key RegisteR

      139
• 6.0 Resets

  141
  • FIGURE 6-1: Reset System Block Diagram

    141
  • 6.1 Resets Resources

    142
    • 6.1.1 Key Resources

      142
  • 6.2 RCON Control Register

    142
    • Register 6-1: RCON: Reset Control Register(1)

      143
• 7.0 Interrupt Controller

  145
  • 7.1 Interrupt Vector Table

    145
  • 7.2 Auxiliary Interrupt Vector

    145
  • 7.3 Reset Sequence

    145
    • FIGURE 7-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Interrupt Vector Table

      146
    • TABLE 7-1: Interrupt Vector Details

      147
  • 7.4 Interrupt Resources

    150
    • 7.4.1 Key Resources

      150
  • 7.5 Interrupt Control and Status Registers

    150
    • 7.5.1 INTCON1 through INTCON4

      150
    • 7.5.2 IFSx

      150
    • 7.5.3 IECx

      150
    • 7.5.4 IPCx

      150
    • 7.5.5 INTTREG

      150
    • 7.5.6 status/Control registers

      150
      • Register 7-1: SR: CPU Status Register(1)

        151
      • Register 7-2: CORCON: Core Control Register(1)

        152
      • Register 7-3: INTCON1: Interrupt Control Register 1

        153
      • Register 7-4: INTCON2: Interrupt Control Register 2

        155
      • Register 7-5: INTCON3: Interrupt Control Register 3

        156
      • Register 7-6: INTCON4: Interrupt Control Register 4

        156
      • Register 7-7: INTTREG: Interrupt Control and Status Register

        157
• 8.0 Direct Memory Access (DMA)

  159
  • FIGURE 8-1: DMA Controller

    159
  • TABLE 8-1: DMA Channel to Peripheral Associations

    160
  • FIGURE 8-2: DMA Controller to Peripheral Associations Block Diagram

    161
  • 8.1 DMA Resources

    162
    • 8.1.1 Key Resources

      162
  • 8.2 DMA Control Registers

    162
    • Register 8-1: DMAxCON: DMA Channel x Control Register

      163
    • Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register

      164
    • Register 8-3: DMAxSTAH: DMA Channel x Start Address Register A (High)

      165
    • Register 8-4: DMAxSTAL: DMA Channel x Start Address Register A (Low)

      165
    • Register 8-5: DMAxSTBH: DMA Channel x Start Address Register B (High)

      166
    • Register 8-6: DMAxSTBL: DMA Channel x Start Address Register B (Low)

      166
    • Register 8-7: DMAxPAD: DMA Channel x Peripheral Address Register(1)

      167
    • Register 8-8: DMAxCNT: DMA Channel x Transfer Count Register(1)

      167
    • Register 8-9: DSADRH: Most Recent DMA Data Space High Address Register

      168
    • Register 8-10: DSADRL: Most Recent DMA Data Space Low Address Register

      168
    • Register 8-11: DMAPWC: DMA Peripheral Write Collision Status Register

      169
    • Register 8-12: DMARQC: DMA Request Collision Status Register

      171
    • Register 8-13: DMALCA: DMA Last Channel Active Status Register

      173
    • Register 8-14: DMAPPS: DMA Ping-Pong Status Register

      174
• 9.0 Oscillator Configuration

  177
  • FIGURE 9-1: Oscillator System Diagram

    178
  • 9.1 CPU Clocking System

    179
    • EQUATION 9-1: Device Operating Frequency

      179
    • FIGURE 9-2: PLL Block Diagram

      179
    • EQUATION 9-2: Fosc Calculation

      179
    • EQUATION 9-3: Fvco Calculation

      179
    • FIGURE 9-3: APLL Block Diagram

      180
    • EQUATION 9-4: Favco Calculation

      180
    • TABLE 9-1: Configuration Bit Values for Clock Selection

      181
  • 9.2 Oscillator Resources

    181
    • 9.2.1 Key Resources

      181
  • 9.3 Oscillator Control Registers

    182
    • Register 9-1: OSCCON: Oscillator Control Register(1,3)

      182
    • Register 9-2: CLKDIV: Clock Divisor Register(2)

      184
    • Register 9-3: PLLFBD: PLL Feedback Divisor Register(1)

      186
    • Register 9-4: OSCTUN: FRC Oscillator Tuning Register(1)

      187
    • Register 9-5: ACLKCON3: Auxiliary Clock Control Register 3(1,2)

      188
    • Register 9-6: ACLKDIV3: Auxiliary Clock Divisor Register 3(1,2)

      189
    • Register 9-7: REFOCON: Reference Oscillator Control Register

      190
• 10.0 Power-Saving Features

  191
  • 10.1 Clock Frequency and Clock Switching

    191
  • 10.2 Instruction-Based Power-Saving Modes

    191
    • 10.2.1 Sleep Mode

      191
      • EXAMPLE 10-1: PWRSAV Instruction Syntax

        191
    • 10.2.2 Idle Mode

      192
    • 10.2.3 Interrupts Coincident with Power Save Instructions

      192
  • 10.3 Doze Mode

    192
  • 10.4 Peripheral Module Disable

    192
  • 10.5 Power-Saving Resources

    193
    • 10.5.1 Key Resources

      193
  • 10.6 Special Function Registers

    193
    • Register 10-1: PMD1: Peripheral Module Disable Control Register 1

      194
    • Register 10-2: PMD2: Peripheral Module Disable Control Register 2

      196
    • Register 10-3: PMD3: Peripheral Module Disable Control Register 3

      198
    • Register 10-4: PMD4: Peripheral Module Disable Control Register 4

      200
    • Register 10-5: PMD5: Peripheral Module Disable Control Register 5

      201
    • Register 10-6: PMD6: Peripheral Module Disable Control Register 6

      203
    • Register 10-7: PMD7: Peripheral Module Disable Control Register 7

      204
• 11.0 I/O Ports

  207
  • 11.1 Parallel I/O (PIO) Ports

    207
    • FIGURE 11-1: Block Diagram of a Typical Shared Port Structure

      208
    • 11.1.1 Open-Drain Configuration

      209
  • 11.2 Configuring Analog and Digital Port Pins

    209
    • 11.2.1 I/O Port Write/Read Timing

      209
  • 11.3 Input Change Notification

    209
    • EXAMPLE 11-1: Port Write/Read Example

      209
  • 11.4 Peripheral Pin Select

    210
    • 11.4.1 Available Pins

      210
    • 11.4.2 Available Peripherals

      210
    • 11.4.3 Controlling Peripheral Pin Select

      210
    • 11.4.4 Input Mapping

      210
      • FIGURE 11-2: U1RX Remappable Input

        210
      • TABLE 11-1: Selectable Input Sources (Maps Input to Function)

        211
      • TABLE 11-2: Input Pin Selection for Selectable Input Sources

        213
      • FIGURE 11-3: Multiplexing of Remappable Output for RPn

        215
      • TABLE 11-3: Output Selection for Remappable Pins (RPn)

        215
      • EXAMPLE 11-2: Connecting IC1 to HOME1 Digital Filter Input on Pin 3 of the dsPIC33EP512MU810 Device

        217
  • 11.5 I/O Helpful Tips

    218
  • 11.6 I/O Resources

    219
    • 11.6.1 Key Resources

      219
  • 11.7 Peripheral Pin Select Control Registers

    220
    • Register 11-1: RPINR0: Peripheral Pin Select Input Register 0

      220
    • Register 11-2: RPINR1: Peripheral Pin Select Input Register 1

      221
    • Register 11-3: RPINR2: Peripheral Pin Select Input Register 2

      222
    • Register 11-4: RPINR3: Peripheral Pin Select Input Register 3

      223
    • Register 11-5: RPINR4: Peripheral Pin Select Input Register 4

      224
    • Register 11-6: RPINR5: Peripheral Pin Select Input Register 5

      225
    • Register 11-7: RPINR6: Peripheral Pin Select Input Register 6

      226
    • Register 11-8: RPINR7: Peripheral Pin Select Input Register 7

      227
    • Register 11-9: RPINR8: Peripheral Pin Select Input Register 8

      228
    • Register 11-10: RPINR9: Peripheral Pin Select Input Register 9

      229
    • Register 11-11: RPINR10: Peripheral Pin Select Input Register 10

      230
    • Register 11-12: RPINR11: Peripheral Pin Select Input Register 11

      231
    • Register 11-13: RPINR12: Peripheral Pin Select Input Register 12 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)

      232
    • Register 11-14: RPINR13: Peripheral Pin Select Input Register 13 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)

      233
    • Register 11-15: RPINR14: Peripheral Pin Select Input Register 14 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)

      234
    • Register 11-16: RPINR15: Peripheral Pin Select Input Register 15 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)

      235
    • Register 11-17: RPINR16: Peripheral Pin Select Input Register 16 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)

      236
    • Register 11-18: RPINR17: Peripheral Pin Select Input Register 17 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)

      237
    • Register 11-19: RPINR18: Peripheral Pin Select Input Register 18

      238
    • Register 11-20: RPINR19: Peripheral Pin Select Input Register 19

      239
    • Register 11-21: RPINR20: Peripheral Pin Select Input Register 20

      240
    • Register 11-22: RPINR21: Peripheral Pin Select Input Register 21

      241
    • Register 11-23: RPINR23: Peripheral Pin Select Input Register 23

      241
    • Register 11-24: RPINR24: Peripheral Pin Select Input Register 24

      242
    • Register 11-25: RPINR25: Peripheral Pin Select Input Register 25

      243
    • Register 11-26: RPINR26: Peripheral Pin Select Input Register 26

      244
    • Register 11-27: RPINR27: Peripheral Pin Select Input Register 27

      245
    • Register 11-28: RPINR28: Peripheral Pin Select Input Register 28

      246
    • Register 11-29: RPINR29: Peripheral Pin Select Input Register 29

      247
    • Register 11-30: RPINR30: Peripheral Pin Select Input Register 30

      248
    • Register 11-31: RPINR31: Peripheral Pin Select Input Register 31

      249
    • Register 11-32: RPINR32: Peripheral Pin Select Input Register 32

      250
    • Register 11-33: RPINR33: Peripheral Pin Select Input Register 33

      251
    • Register 11-34: RPINR34: Peripheral Pin Select Input Register 34

      252
    • Register 11-35: RPINR35: Peripheral Pin Select Input Register 35

      253
    • Register 11-36: RPINR36: Peripheral Pin Select Input Register 36

      254
    • Register 11-37: RPINR37: Peripheral Pin Select Input Register 37

      255
    • Register 11-38: RPINR38: Peripheral Pin Select Input Register 38

      256
    • Register 11-39: RPINR39: Peripheral Pin Select Input Register 39

      257
    • Register 11-40: RPINR40: Peripheral Pin Select Input Register 40

      258
    • Register 11-41: RPINR41: Peripheral Pin Select Input Register 41

      259
    • Register 11-42: RPINR42: Peripheral Pin Select Input Register 42

      260
    • Register 11-43: RPINR43: Peripheral Pin Select Input Register 43

      261
    • Register 11-44: RPOR0: Peripheral Pin Select Output Register 0

      261
    • Register 11-45: RPOR1: Peripheral Pin Select Output Register 1

      262
    • Register 11-46: RPOR2: Peripheral Pin Select Output Register 2

      262
    • Register 11-47: RPOR3: Peripheral Pin Select Output Register 3

      263
    • Register 11-48: RPOR4: Peripheral Pin Select Output Register 4

      263
    • Register 11-49: RPOR5: Peripheral Pin Select Output Register 5

      264
    • Register 11-50: RPOR6: Peripheral Pin Select Output Register 6

      264
    • Register 11-51: RPOR7: Peripheral Pin Select Output Register 7

      265
    • Register 11-52: RPOR8: Peripheral Pin Select Output Register 8

      265
    • Register 11-53: RPOR9: Peripheral Pin Select Output Register 9

      266
    • Register 11-54: RPOR10: Peripheral Pin Select Output Register 10

      266
    • Register 11-55: RPOR11: Peripheral Pin Select Output Register 11

      267
    • Register 11-56: RPOR12: Peripheral Pin Select Output Register 12

      267
    • Register 11-57: RPOR13: Peripheral Pin Select Output Register 13

      268
    • Register 11-58: RPOR14: Peripheral Pin Select Output Register 14

      268
    • Register 11-59: RPOR15: Peripheral Pin Select Output Register 15

      269
• 12.0 Timer1

  271
  • TABLE 12-1: Timer Mode Settings

    271
  • FIGURE 12-1: 16-Bit Timer1 Module Block Diagram

    271
  • 12.1 Timer Resources

    272
    • 12.1.1 Key Resources

      272
  • 12.2 Timer1 Control Register

    273
    • Register 12-1: T1CON: Timer1 Control Register

      273
• 13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9

  275
  • FIGURE 13-1: Type B Timerx block Diagram (x = 2, 4, 6 and 8)

    276
  • FIGURE 13-2: Type C Timerx Block Diagram (x = 3, 5, 7 and 9)

    276
  • FIGURE 13-3: Type B/Type C Timer Pair Block Diagram (32-bit Timer)

    277
  • 13.1 Timer Resources

    277
    • 13.1.1 Key Resources

      277
  • 13.2 Timerx/y Control Registers

    278
    • Register 13-1: TxCON: (T2CON, T4CON, T6CON or T8CON) Control Register

      278
    • Register 13-2: TyCON: (T3CON, T5CON, T7CON or T9CON) Control Register

      279
• 14.0 Input Capture

  281
  • FIGURE 14-1: Input Capture Module Block Diagram

    281
  • 14.1 Input Capture Resources

    282
    • 14.1.1 Key Resources

      282
  • 14.2 Input Capture Control Registers

    283
    • Register 14-1: ICxCON1: Input Capture X Control Register 1

      283
    • Register 14-2: ICxCON2: Input Capture X Control Register 2

      284
• 15.0 Output Compare

  287
  • FIGURE 15-1: Output Compare Module Block Diagram

    287
  • 15.1 Output Compare Resources

    288
    • 15.1.1 Key Resources

      288
  • 15.2 Output Compare Control Registers

    289
    • Register 15-1: OCxCON1: Output Compare x Control Register 1

      289
    • Register 15-2: OCxCON2: Output Compare x Control Register 2

      291
• 16.0 High-Speed PWM Module (dsPIC33EPXXX(MC/MU)8XX Devices Only)

  293
  • FIGURE 16-1: High-Speed PWM Module Architectural Overview

    294
  • FIGURE 16-2: High-Speed PWM MOdule Register Interconnection Diagram

    295
  • 16.1 PWM Resources

    296
    • 16.1.1 Key Resources

      296
  • 16.2 PWM Control Registers

    297
    • Register 16-1: PTCON: PWM Time Base Control Register

      297
    • Register 16-2: PTCON2: PWM Primary Master Clock Divider Select Register 2

      299
    • Register 16-3: PTPER: Primary Master Time Base Period Register

      299
    • Register 16-4: SEVTCMP: PWM Primary Special Event Compare Register

      300
    • Register 16-5: STCON: PWM Secondary Master Time Base Control Register

      301
    • Register 16-6: STCON2: PWM Secondary Clock Divider Select Register 2

      302
    • Register 16-7: STPER: Secondary Master Time Base Period Register(1)

      302
    • Register 16-8: SSEVTCMP: PWM Secondary Special Event Compare Register

      303
    • Register 16-9: CHOP: PWM Chop Clock Generator Register

      303
    • Register 16-10: MDC: PWM Master Duty Cycle Register

      304
    • Register 16-11: PWMCONx: PWMx Control Register

      305
    • Register 16-12: PDCx: PWMx Generator Duty Cycle Register(1)

      307
    • Register 16-13: SDCx: PWMx Secondary Duty Cycle Register(1)

      307
    • Register 16-14: PHASEx: PWMx Primary Phase Shift Register(1,2)

      308
    • Register 16-15: SPHASEx: PWMx Secondary Phase Shift Register(1,2)

      309
    • Register 16-16: DTRx: PWMx Dead-Time Register

      310
    • Register 16-17: ALTDTRx: PWMx Alternate Dead-Time Register

      310
    • Register 16-18: TRGCONx: PWMx Trigger Control Register

      311
    • Register 16-19: IOCONx: PWMx I/O Control Register

      312
    • Register 16-20: TRIGx: PWMx Primary Trigger Compare Value Register

      314
    • Register 16-21: FCLCONx: PWMx Fault Current-Limit Control Register

      315
    • Register 16-22: LEBCONx: Leading-Edge Blanking Control Register x

      317
    • Register 16-23: LEBDLYx: Leading-Edge Blanking Delay Register x

      318
    • Register 16-24: AUXCONx: PWM Auxiliary Control Register x

      319
    • Register 16-25: PWMCAPx: Primary PWMx Time Base Capture Register

      320
• 17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXX(MC/MU)8XX Devices Only)

  321
  • FIGURE 17-1: QEI Block Diagram

    322
  • 17.1 QEI Resources

    323
    • 17.1.1 Key Resources

      323
  • 17.2 QEI Control Registers

    324
    • Register 17-1: QEIxCON: QEIx Control Register

      324
    • Register 17-2: QEIxIOC: QEIx I/O Control Register

      326
    • Register 17-3: QEIxSTAT: QEIx Status register

      328
    • Register 17-4: POSxCNTH: Position Counter x High Word Register

      330
    • Register 17-5: POSxCNTL: Position Counter x Low Word Register

      330
    • Register 17-6: POSxHLD: Position Counter x Hold Register

      330
    • Register 17-7: VELxCNT: Velocity Counter x Register

      331
    • Register 17-8: INDXxCNTH: Index Counter x High Word Register

      331
    • Register 17-9: INDXxCNTL: Index Counter x Low Word Register

      331
    • Register 17-10: INDXxHLD: Index Counter x Hold Register

      332
    • Register 17-11: QEIxICH: QEIx Initialization/Capture High Word Register

      332
    • Register 17-12: QEIxICL: QEIx Initialization/Capture Low Word Register

      332
    • Register 17-13: QEIxLECH: QEIx Less Than or Equal Compare High Word Register

      333
    • Register 17-14: QEIxLECL: QEIx Less Than or Equal Compare Low Word Register

      333
    • Register 17-15: QEIxGECH: QEIx Greater Than or Equal Compare High Word Register

      334
    • Register 17-16: QEIxGECL: QEIx Greater Than or Equal Compare Low Word Register

      334
    • Register 17-17: INTxTMRH: Interval Timer x High Word Register

      334
    • Register 17-18: INTxTMRL: INterval Timer x Low Word Register

      335
    • Register 17-19: INTxHLDH: Interval Timer x Hold High Word Register

      335
    • Register 17-20: INTxHLDL: Interval Timer x Hold Low Word Register

      335
• 18.0 Serial Peripheral Interface (SPI)

  337
  • FIGURE 18-1: SPIx Module Block Diagram

    337
  • 18.1 SPI Helpful Tips

    338
  • 18.2 SPI Resources

    338
    • 18.2.1 Key Resources

      338
  • 18.3 SPI Control Registers

    339
    • Register 18-1: SPIxSTAT: SPIx Status and Control Register

      339
    • Register 18-2: SPIxCON1: SPIx Control Register 1

      341
    • Register 18-3: SPIxCON2: SPIx Control Register 2

      343
• 19.0 Inter-Integrated Circuit™ (I2C™)

  345
  • FIGURE 19-1: I2C™ Block Diagram (x = 1 or 2)

    346
  • 19.1 I2C Resources

    347
    • 19.1.1 Key Resources

      347
  • 19.2 I2C Control Registers

    348
    • Register 19-1: I2CxCON: I2Cx Control Register

      348
    • Register 19-2: I2CxSTAT: I2Cx Status Register

      350
    • Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      352
• 20.0 Universal Asynchronous Receiver Transmitter (UART)

  353
  • FIGURE 20-1: UARTx Simplified Block Diagram

    353
  • 20.1 UARTx Helpful Tips

    354
  • 20.2 UARTx Resources

    354
    • 20.2.1 Key Resources

      354
  • 20.3 UARTx Registers

    355
    • Register 20-1: UxMODE: UARTx Mode Register

      355
    • Register 20-2: UxSTA: UARTx Status and Control Register

      357
• 21.0 Enhanced CAN (ECAN™) Module

  359
  • 21.1 Overview

    359
    • FIGURE 21-1: ECANx Module Block Diagram

      360
  • 21.2 Modes of Operation

    361
  • 21.3 ECAN Resources

    361
    • 21.3.1 Key Resources

      361
  • 21.4 ECANx Control Registers

    362
    • Register 21-1: CxCTRL1: ECANx CONTROL REGISTER 1

      362
    • Register 21-2: CxCTRL2: ECANx Control Register 2

      363
    • Register 21-3: CxVEC: ECANx Interrupt Code Register

      364
    • Register 21-4: CxFCTRL: ECANx FIFO Control Register

      365
    • Register 21-5: CxFIFO: ECANx FIFO Status Register

      366
    • Register 21-6: CxINTF: ECANx Interrupt Flag Register

      367
    • Register 21-7: CxINTE: ECANx Interrupt Enable Register

      368
    • Register 21-8: CxEC: ECANx Transmit/Receive Error Count Register

      369
    • Register 21-9: CxCFG1: ECANx Baud Rate Configuration Register 1

      369
    • Register 21-10: CxCFG2: ECANx Baud Rate Configuration Register 2

      370
    • Register 21-11: CxFEN1: ECANx Acceptance Filter Enable Register 1

      371
    • Register 21-12: CxBUFPNT1: ECANx Filter 0-3 Buffer Pointer Register 1

      371
    • Register 21-13: CxBUFPNT2: ECANx Filter 4-7 Buffer Pointer Register 2

      372
    • Register 21-14: CxBUFPNT3: ECANx Filter 8-11 Buffer Pointer Register 3

      372
    • Register 21-15: CxBUFPNT4: ECANx Filter 12-15 Buffer Pointer Register 4

      373
    • Register 21-16: CxRXFnSID: ECANx Acceptance Filter n Standard Identifier Register n (n = 0-15)

      374
    • Register 21-17: CxRXFnEID: ECANx Acceptance Filter n Extended Identifier Register n (n = 0-15)

      375
    • Register 21-18: CxFMSKSEL1: ECANx Filter 7-0 Mask Selection Register

      375
    • Register 21-19: CxFMSKSEL2: ECANx Filter 15-8 Mask Selection Register

      376
    • Register 21-20: CxRXMnSID: ECANx Acceptance Filter Mask n Standard Identifier Register n (n = 0-2)

      377
    • Register 21-21: CxRXMnEID: ECANx Acceptance Filter Mask n Extended Identifier Register n (n = 0-2)

      377
    • Register 21-22: CxRXFUL1: ECANx Receive Buffer Full Register 1

      378
    • Register 21-23: CxRXFUL2: ECANx Receive Buffer Full Register 2

      378
    • Register 21-24: CxRXOVF1: ECANx Receive Buffer Overflow Register 1

      379
    • Register 21-25: CxRXOVF2: ECANx Receive Buffer Overflow Register 2

      379
    • Register 21-26: CxTRmnCON: ECANx TX/RX Buffer m Control Register (m = 0, 2, 4, 6; n = 1, 3, 5, 7)

      380
  • 21.5 ECAN Message Buffers

    381
• 22.0 USB On-The-Go (OTG) Module (dsPIC33EPXXXMU8XX and PIC24EPGU8XX Devices Only)

  385
  • 22.1 Overview

    385
  • 22.2 Clearing USB OTG Interrupts

    385
    • FIGURE 22-1: USB Interface Diagram

      386
  • 22.3 USB OTG Resources

    387
    • 22.3.1 Key Resources

      387
  • 22.4 USB Control Registers

    388
    • Register 22-1: UxOTGSTAT: USB OTG Status Register

      388
    • Register 22-2: UxOTGCON: USB On-The-Go Control Register

      389
    • Register 22-3: UxPWRC: USB Power Control Register

      390
    • Register 22-4: UxSTAT: USB Status Register

      391
    • Register 22-5: UxCON: USB Control Register (Device mode)

      392
    • Register 22-6: UxCON: USB Control Register (Host mode)

      393
    • Register 22-7: UxADDR: USB Address Register

      394
    • Register 22-8: UxTOK: USB Token Register (Host mode only)

      394
    • Register 22-9: UxSOF: USB OTG Start-Of-Token Threshold Register (Host mode only)

      395
    • Register 22-10: UxCNFG1: USB Configuration Register 1

      395
    • Register 22-11: UxCNFG2: USB Configuration Register 2

      396
    • Register 22-12: UxOTGIR: USB OTG Interrupt Status Register (Host mode only)

      397
    • Register 22-13: UxOTGIE: USB OTG Interrupt Enable Register (Host mode only)

      398
    • Register 22-14: UxIR: USB Interrupt Status Register (Device mode only)

      399
    • Register 22-15: UxIR: USB Interrupt Status Register (Host mode only)

      400
    • Register 22-16: UxIE: USB Interrupt Enable Register (Device mode)

      401
    • Register 22-17: UxIE: USB Interrupt Enable Register (Host mode)

      402
    • Register 22-18: UxEIR: USB Error Interrupt Status Register (Device mode)

      403
    • Register 22-19: UxEIR: USB Error Interrupt Status Register (Host mode)

      404
    • Register 22-20: UxEIE: USB Error Interrupt Enable Register (Device mode)

      405
    • Register 22-21: UxEIE: USB Error Interrupt Enable Register (Host mode)

      406
    • Register 22-22: UxEPn: USB Endpoint n Control Registers (n = 0 to 15)

      407
    • Register 22-23: UxBDTP1: USB Buffer Description Table Register 1

      408
    • Register 22-24: UxBDTP2: USB Buffer Description Table Register 2

      408
    • Register 22-25: UxBDTP3: USB Buffer Description Table Register 3

      409
    • Register 22-26: UxPWMCON: USB Vbus PWM Generator Control Register

      409
    • Register 22-27: UxPWMRRS: Duty Cycle and PWM Period Register

      410
    • Register 22-28: UxFRMH: USB Frame Number High Register

      410
    • Register 22-29: UxFRML: USB Frame Number Low Register

      411
• 23.0 10-Bit/12-Bit Analog-to- Digital Converter (ADC)

  413
  • 23.1 Key Features

    413
    • FIGURE 23-1: ADCx Module Block Diagram

      414
    • FIGURE 23-2: ADCx Conversion Clock Period Block Diagram

      415
  • 23.2 ADC Helpful Tips

    416
  • 23.3 ADC Resources

    416
    • 23.3.1 Key Resources

      416
  • 23.4 ADC Control Registers

    417
    • Register 23-1: ADxCON1: ADCx Control Register 1

      417
    • Register 23-2: AD1CON2: ADC1 Control Register 2

      419
    • Register 23-3: AD2CON2: ADC2 Control Register 2

      421
    • Register 23-4: ADxCON3: ADCx Control Register 3

      423
    • Register 23-5: ADxCON4: ADCx Control Register 4

      424
    • Register 23-6: ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register

      425
    • Register 23-7: ADxCHS0: ADCx Input Channel 0 Select Register

      426
    • Register 23-8: AD1CSSH: ADC1 Input Scan Select Register High(1,2,3)

      427
    • Register 23-9: ADxCSSL: ADCx Input Scan Select Register Low(1,2)

      427
• 24.0 Data Converter Interface (DCI) Module

  429
  • 24.1 Module Introduction

    429
    • FIGURE 24-1: DCI Module Block Diagram

      429
  • 24.2 DCI Resources

    430
    • 24.2.1 Key Resources

      430
  • 24.3 DCI Control Registers

    431
    • Register 24-1: DCICON1: DCI Control Register 1

      431
    • Register 24-2: DCICON2: DCI Control Register 2

      432
    • Register 24-3: DCICON3: DCI Control Register 3

      433
    • Register 24-4: DCISTAT: DCI Status Register

      434
    • Register 24-5: RSCON: DCI Receive Slot Control Register

      435
    • Register 24-6: TSCON: DCI Transmit Slot Control Register

      435
• 25.0 Comparator Module

  437
  • FIGURE 25-1: Comparator I/O Operating Modes

    437
  • FIGURE 25-2: Comparator Voltage Reference Block Diagram

    438
  • FIGURE 25-3: User-Programmable Blanking Function Block Diagram

    438
  • FIGURE 25-4: Digital Filter Interconnect Block Diagram

    439
  • 25.1 Comparator Resources

    439
    • 25.1.1 Key Resources

      439
  • 25.2 Comparator Control Registers

    440
    • Register 25-1: CMSTAT: Comparator Status Register

      440
    • Register 25-2: CMxCON: Comparator x Control Register

      441
    • Register 25-3: CMxMSKSRC: Comparator x Mask Source Select Control Register

      443
    • Register 25-4: CMxMSKCON: Comparator x Mask Gating Control Register

      445
    • Register 25-5: CMxFLTR: Comparator x Filter Control Register

      447
    • Register 25-6: CVRCON: Comparator Voltage Reference Control Register

      448
• 26.0 Real-Time Clock and Calendar (RTCC)

  449
  • FIGURE 26-1: RTCC Block Diagram

    450
  • 26.1 Writing to the RTCC Timer

    451
  • 26.2 RTCC Resources

    451
    • 26.2.1 Key Resources

      451
  • 26.3 RTCC Registers

    452
    • Register 26-1: RCFGCAL: RTCC Calibration and Configuration Register(1)

      452
    • Register 26-2: PADCFG1: Pad Configuration Control Register

      454
    • Register 26-3: ALCFGRPT: Alarm Configuration Register

      455
    • Register 26-4: RTCVAL (when RTCPTR<1:0> = 11): YEAR VALUE Register(1)

      456
    • Register 26-5: RTCVAL (when RTCPTR<1:0> = 10): MONTH AND DAY VALUE Register(1)

      456
    • Register 26-6: RTCVAL (when RTCPTR<1:0> = 01): Weekday and Hours Value Register(1)

      457
    • Register 26-7: RTCVAL (when RTCPTR<1:0> = 00): Minutes and Seconds Value Register

      457
    • Register 26-8: ALRMVAL (when ALRMPTR<1:0> = 10): Alarm Month and Day Value Register(1)

      458
    • Register 26-9: ALRMVAL (when ALRMPTR<1:0> = 01): Alarm Weekday and Hours Value Register(1)

      459
    • Register 26-10: ALRMVAL (when ALRMPTR<1:0> = 00): Alarm Minutes and Seconds Value Register

      460
• 27.0 Programmable Cyclic Redundancy Check (CRC) Generator

  461
  • FIGURE 27-1: Programmable CRC Block Diagram

    461
  • FIGURE 27-2: CRC Shift Engine Detail

    461
  • 27.1 Overview

    462
    • TABLE 27-1: CRC SETUP EXAMPLEs FOR 16 and 32-bit polynomial

      462
  • 27.2 Programmable CRC Resources

    462
    • 27.2.1 Key Resources

      462
  • 27.3 Programmable CRC Registers

    463
    • Register 27-1: CRCCON1: CRC Control Register 1

      463
    • Register 27-2: CRCCON2: CRC Control Register 2

      464
    • Register 27-3: CRCXORH: CRC XOR Polynomial HIGH Register

      465
    • Register 27-4: CRCXORL: CRC XOR Polynomial Low Register

      465
• 28.0 Parallel Master Port (PMP)

  467
  • FIGURE 28-1: PMP Module Pinout and Connections to External Devices

    467
  • 28.1 PMP Resources

    468
    • 28.1.1 Key Resources

      468
  • 28.2 PMP Control Registers

    469
    • Register 28-1: PMCON: Parallel Master Port Control Register

      469
    • Register 28-2: PMMODE: Parallel Master Port Mode Register

      471
    • Register 28-3: PMADDR: Parallel Master Port Address Register (Master modes only)(1)

      473
    • Register 28-4: PMAEN: Parallel Master Port Address Enable Register

      474
    • Register 28-5: PMSTAT: Parallel Master Port Status Register (Slave mode only)

      475
    • Register 28-6: PADCFG1: Pad Configuration Control Register

      476
• 29.0 Special Features

  477
  • 29.1 Configuration Bits

    477
    • TABLE 29-1: Device Configuration Register Map

      477
    • TABLE 29-2: Configuration Bits Description

      478
  • 29.2 On-Chip Voltage Regulator

    481
    • FIGURE 29-1: Connections for the On-Chip Voltage Regulator(1,2,3)

      481
  • 29.3 Brown-out Reset (BOR)

    481
  • 29.4 Watchdog Timer (WDT)

    482
    • 29.4.1 Prescaler/Postscaler

      482
    • 29.4.2 Sleep and Idle Modes

      482
    • 29.4.3 Enabling WDT

      482
      • FIGURE 29-2: WDT Block diagram

        482
  • 29.5 JTAG Interface

    483
  • 29.6 In-Circuit Serial Programming

    483
  • 29.7 In-Circuit Debugger

    483
  • 29.8 Code Protection and CodeGuard™ Security

    483
• 30.0 Instruction Set Summary

  485
  • TABLE 30-1: Symbols used in Opcode Descriptions

    486
  • TABLE 30-2: Instruction Set Overview

    488
• 31.0 Development Support

  495
  • 31.1 MPLAB Integrated Development Environment Software

    495
  • 31.2 MPLAB C Compilers for Various Device Families

    496
  • 31.3 HI-TECH C for Various Device Families

    496
  • 31.4 MPASM Assembler

    496
  • 31.5 MPLINK Object Linker/ MPLIB Object Librarian

    496
  • 31.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    496
  • 31.7 MPLAB SIM Software Simulator

    497
  • 31.8 MPLAB REAL ICE In-Circuit Emulator System

    497
  • 31.9 MPLAB ICD 3 In-Circuit Debugger System

    497
  • 31.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    497
  • 31.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    498
  • 31.12 MPLAB PM3 Device Programmer

    498
  • 31.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    498
• 32.0 Electrical Characteristics

  499
  • Absolute Maximum Ratings

    499
  • 32.1 DC Characteristics

    500
    • TABLE 32-1: Operating MIPS vs. Voltage

      500
    • TABLE 32-2: Thermal Operating Conditions

      500
    • TABLE 32-3: Thermal Packaging Characteristics

      500
    • TABLE 32-4: DC Temperature and Voltage specifications

      501
    • TABLE 32-5: DC Characteristics: Operating Current (Idd)

      502
    • TABLE 32-6: DC Characteristics: Idle Current (iidle)

      503
    • TABLE 32-7: DC Characteristics: Power-Down Current (Ipd)

      504
    • TABLE 32-8: DC Characteristics: doze Current (Idoze)(1)

      505
    • TABLE 32-9: DC Characteristics: I/O Pin Input Specifications

      506
    • TABLE 32-10: DC Characteristics: I/O Pin Output Specifications

      509
    • TABLE 32-11: Electrical Characteristics: BOR

      509
    • TABLE 32-12: DC Characteristics: Program Memory

      510
    • TABLE 32-13: Internal Voltage Regulator Specifications

      510
  • 32.2 AC Characteristics and Timing Parameters

    511
    • TABLE 32-14: Temperature and Voltage Specifications – AC

      511
    • FIGURE 32-1: Load Conditions for Device Timing Specifications

      511
    • TABLE 32-15: Capacitive Loading Requirements on Output Pins

      511
    • FIGURE 32-2: External Clock Timing

      512
    • TABLE 32-16: External Clock Timing Requirements

      512
    • TABLE 32-17: PLL Clock Timing Specifications

      513
    • TABLE 32-18: Auxiliary PLL Clock Timing SpecificationS (dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX Devices Only)

      513
    • TABLE 32-19: Internal FRC Accuracy

      514
    • TABLE 32-20: Internal LPRC accuracy

      514
    • FIGURE 32-3: I/O Timing Characteristics

      515
    • TABLE 32-21: I/O Timing Requirements

      515
    • FIGURE 32-4: Power-On Reset Timing Characteristics

      516
    • FIGURE 32-5: BOR and Master Clear Reset Timing Characteristics

      517
    • TABLE 32-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements

      517
    • FIGURE 32-6: Timer1-Timer9 External Clock Timing Characteristics

      518
    • TABLE 32-23: Timer1 External Clock Timing Requirements(1)

      518
    • TABLE 32-24: Timer2, Timer4, Timer6, Timer8 (TYPe B Timer) External Clock Timing Requirements

      519
    • TABLE 32-25: Timer3, Timer5, Timer7, Timer9 (Type C Timer) External Clock Timing Requirements

      519
    • FIGURE 32-7: TimerQ (QEI Module) External Clock Timing Characteristics

      520
    • TABLE 32-26: QEI module External Clock Timing Requirements

      520
    • FIGURE 32-8: INPUT CAPTURE (ICx) TIMING Characteristics

      521
    • Table 32-27: Input Capture Module (ICx) Timing Requirements

      521
    • FIGURE 32-9: Output Compare Module (OCx) Timing Characteristics

      522
    • TABLE 32-28: Output Compare Module (OCx) timing requirements

      522
    • FIGURE 32-10: OCx/PWMx Module Timing Characteristics

      522
    • TABLE 32-29: OCx/PWMx MODE Timing Requirements

      522
    • FIGURE 32-11: High-Speed PWMx Module fault Timing Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)

      523
    • FIGURE 32-12: High-Speed PWMx Module Timing Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)

      523
    • TABLE 32-30: High-Speed PWMx Module Timing Requirements (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)

      523
    • FIGURE 32-13: QEA/QEB Input Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)

      524
    • TABLE 32-31: Quadrature Decoder Timing Requirements (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)

      524
    • FIGURE 32-14: QEI Module Index Pulse Timing Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)

      525
    • TABLE 32-32: QEI INDEX PULSE Timing Requirements (dsPIC33EPXXX(MC/MU)MU806/810/814 Devices Only)

      525
    • TABLE 32-33: SPI1, SPI3 and SPI4 Maximum Data/CLock Rate Summary

      526
    • FIGURE 32-15: SPI1, SPI3 and SPI4 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS

      526
    • FIGURE 32-16: SPI1, SPI3 and SPI4 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS

      527
    • TABLE 32-34: SPI1, SPI3 and SPI4 Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      527
    • FIGURE 32-17: SPI1, SPI3 and SPI4 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      528
    • TABLE 32-35: SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      528
    • FIGURE 32-18: SPI1, SPI3 and SPI4 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      529
    • TABLE 32-36: SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      529
    • FIGURE 32-19: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      530
    • TABLE 32-37: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      531
    • FIGURE 32-20: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      532
    • TABLE 32-38: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      533
    • FIGURE 32-21: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      534
    • TABLE 32-39: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      535
    • FIGURE 32-22: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      536
    • TABLE 32-40: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      537
    • TABLE 32-41: SPI2 Maximum Data/CLock Rate Summary

      538
    • FIGURE 32-23: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS

      538
    • FIGURE 32-24: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS

      539
    • TABLE 32-42: SPI2 Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      539
    • FIGURE 32-25: SPI2 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      540
    • TABLE 32-43: SPI2 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      540
    • FIGURE 32-26: SPI2 MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS

      541
    • TABLE 32-44: SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      541
    • FIGURE 32-27: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      542
    • TABLE 32-45: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      543
    • FIGURE 32-28: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      544
    • TABLE 32-46: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      545
    • FIGURE 32-29: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      546
    • TABLE 32-47: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      547
    • FIGURE 32-30: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      548
    • TABLE 32-48: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      549
    • FIGURE 32-31: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      550
    • FIGURE 32-32: I2Cx Bus Data Timing Characteristics (Master mode)

      550
    • TABLE 32-49: I2Cx Bus Data Timing Requirements (Master Mode)

      551
    • FIGURE 32-33: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)

      552
    • FIGURE 32-34: I2Cx Bus Data Timing Characteristics (slave mode)

      552
    • TABLE 32-50: I2Cx Bus Data Timing Requirements (Slave Mode)

      553
    • FIGURE 32-35: ECAN™ Module I/O Timing Characteristics

      554
    • TABLE 32-51: ECAN™ Module I/O Timing Requirements

      554
    • FIGURE 32-36: UARTx Module I/O Timing Characteristics

      554
    • TABLE 32-52: UARTx Module I/O Timing Requirements

      554
    • TABLE 32-53: USB OTG Module Specifications (dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX Devices Only)

      555
    • TABLE 32-54: ADC Module Specifications

      556
    • TABLE 32-55: ADC Module Specifications (12-Bit Mode)

      557
    • TABLE 32-56: ADC Module Specifications (10-Bit Mode)

      558
    • FIGURE 32-37: ADC Conversion (12-Bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000, SSRCG = 0)

      559
    • TABLE 32-57: ADC Conversion (12-Bit Mode) TiminG rEQUIREMENTS

      560
    • FIGURE 32-38: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000, SSRCG = 0)

      561
    • FIGURE 32-39: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010)

      561
    • TABLE 32-58: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS

      562
    • FIGURE 32-40: DCI Module (Multi-channel, I2S modes) Timing Characteristics

      563
    • TABLE 32-59: DCI Module (Multi-channel, I2S modes) Timing Requirements

      564
    • FIGURE 32-41: DCI Module (AC-link mode) Timing Characteristics

      565
    • TABLE 32-60: DCI Module (AC-Link Mode) Timing Requirements

      566
    • TABLE 32-61: Comparator Timing Specifications

      567
    • TABLE 32-62: Comparator Module Specifications

      567
    • TABLE 32-63: Comparator Reference Voltage Settling Time Specifications

      568
    • TABLE 32-64: Comparator Reference Voltage Specifications

      568
    • Figure 32-42: Parallel Slave Port Timing

      569
    • TABLE 32-65: Parallel Slave Port Timing Specifications

      569
    • FIGURE 32-43: Parallel Master Port Read Timing DiAgram

      570
    • TABLE 32-66: Parallel Master Port Read Timing Requirements

      570
    • FIGURE 32-44: Parallel Master Port Write Timing Diagram

      571
    • TABLE 32-67: Parallel Master Port Write Timing Requirements

      571
    • TABLE 32-68: DMA Module Timing Requirements

      571
• 33.0 DC and AC Device Characteristics Graphs

  573
  • FIGURE 33-1: Voh – 4x Driver Pins @ +85ºC

    573
  • FIGURE 33-2: Voh – 8x Driver Pins @ +85ºC

    573
  • FIGURE 33-3: Vol – 4x Driver Pins @ +85ºC

    573
  • FIGURE 33-4: Vol – 8x Driver Pins @ +85ºC

    573
  • FIGURE 33-5: Typical Ipd Current @ Vdd = 3.3V

    574
  • FIGURE 33-6: Typical Idd Current – Vdd = 3.3V @ +85ºC

    574
  • FIGURE 33-7: Typical Idoze Current @ Vdd = 3.3V

    574
  • FIGURE 33-8: Typical Iidle Current – Vdd = 3.3V @ +85ºC

    574
  • FIGURE 33-9: Typical FRC Frequency @ Vdd = 3.3V

    575
  • FIGURE 33-10: Typical LPRC Frequency @ Vdd = 3.3V

    575
• 34.0 Packaging Information

  577
  • 34.1 Package Marking Information

    577
  • 34.1 Package Marking Information (Continued)

    578
  • 34.2 Package Details

    579
• Appendix A: Revision History

  597
  • Revision A (December 2009)

    597
  • Revision B (July 2010)

    597
    • TABLE A-1: Major Section Updates

      597
  • Revision C (May 2011)

    601
    • TABLE A-2: Major Section Updates

      601
  • Revision D (August 2011)

    603
    • TABLE A-3: Major Section Updates

      603
  • Revision E (August 2011)

    605
  • Revision F (February 2012)

    606
    • TABLE A-4: Major Section Updates

      606
  • Revision G (October 2012)

    607
• INDEX

  609
• The Microchip Web Site

  617
• Customer Change Notification Service

  617
• Customer Support

  617
• Reader Response

  618
• Product Identification System

  619
• Worldwide Sales and Service

  622