データシート目次Operating Conditions1Core: 16-Bit dsPIC33E/PIC24E CPU1Clock Management1Power Management1High-Speed PWM1Advanced Analog Features1Timers/Output Compare/Input Capture1Communication Interfaces1Direct Memory Access (DMA)1Input/Output1Qualification and Class B Support1Debugger Development Support1dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Product Families2TABLE 1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Controller Families2Pin Diagrams3Pin Diagrams4Pin Diagrams5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Pin Diagrams (Continued)10Pin Diagrams (Continued)11TABLE 2: Pin Names: dsPIC33EP256MU810 and dsPIC33EP512MU810 dEVICES(1,2)12Pin Diagrams (Continued)14TABLE 3: Pin Names: PIC24EP256GU810 AND PIC24EP512GU810 dEVICES(1,2)15Pin Diagrams (Continued)17Pin Diagrams (Continued)18Table of Contents19Most Current Data Sheet20Errata20Customer Notification System20Referenced Sources211.0 Device Overview23FIGURE 1-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Block Diagram24TABLE 1-1: Pinout I/O Descriptions252.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers and Microcontrollers312.1 Basic Connection Requirements312.2 Decoupling Capacitors31FIGURE 2-1: Recommended Minimum connection322.2.1 Tank Capacitors322.3 CPU Logic Filter Capacitor Connection (Vcap)322.4 Master Clear (MCLR) Pin32FIGURE 2-2: Example of MCLR Pin Connections322.5 ICSP Pins332.6 External Oscillator Pins33FIGURE 2-3: Suggested Placement of the Oscillator Circuit332.7 Oscillator Value Conditions on Device Start-up332.8 Unused I/Os332.9 Application Examples34FIGURE 2-4: Boost Converter Implementation34FIGURE 2-5: Single-Phase Synchronous Buck converter35FIGURE 2-6: Multi-Phase Synchronous Buck converter35FIGURE 2-7: Interleaved PFC36FIGURE 2-8: BEMF voltage measured using the ADC Module363.0 CPU373.1 Registers373.2 Instruction Set373.3 Data Space Addressing373.4 Addressing Modes37FIGURE 3-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 CPU Block Diagram383.5 Programmer’s Model39TABLE 3-1: Programmer’s Model Register Descriptions39FIGURE 3-2: Programmer’s Model403.6 CPU Resources413.6.1 Key Resources413.7 CPU Control Registers42Register 3-1: SR: CPU Status Register42Register 3-2: CORCON: Core Control Register443.8 Arithmetic Logic Unit (ALU)463.8.1 Multiplier463.8.2 Divider463.9 DSP Engine (dsPIC33EPXXX(GP/ MC/MU)806/810/814 Devices Only)46TABLE 3-2: DSP Instructions Summary464.0 Memory Organization474.1 Program Address Space47FIGURE 4-1: Program Memory Map for dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Devices(1)474.1.1 Program Memory Organization484.1.2 Interrupt and Trap Vectors48FIGURE 4-2: Program Memory Organization484.2 Data Address Space494.2.1 Data Space Width494.2.2 Data Memory Organization and Alignment494.2.3 SFR Space494.2.4 Near Data Space49FIGURE 4-3: Data Memory Map for dsPIC33EP512(GP/MC/MU)806/810/814 Devices with 52-Kbyte RAM50FIGURE 4-4: Data Memory Map for PIC24EP512(GP/GU)806/810/814 Devices with 52-Kbyte RAM51FIGURE 4-5: Data Memory Map for dsPIC33EP256MU806/810/814 Devices with 28-Kbyte RAM52FIGURE 4-6: Data Memory Map for PIC24EP256GU810/814 Devices with 28-Kbyte RAM534.2.5 X and Y Data Spaces544.2.6 DMA RAM544.3 Program Memory Resources544.3.1 Key Resources544.4 Special Function Register Maps54TABLE 4-1: CPU Core Register Map for dsPIC33EPXXX(GP/MC/MU)806/810/814 Devices Only55TABLE 4-2: CPU Core Register Map for PIC24EPXXX(GP/GU)810/814 Devices Only57TABLE 4-3: Interrupt Controller Register Map for dsPIC33EPXXXMU814 Devices Only58TABLE 4-4: Interrupt Controller Register Map for dsPIC33EPXXXMU810 Devices Only60TABLE 4-5: Interrupt Controller Register Map for dsPIC33EPXXXMU806 Devices Only62TABLE 4-6: Interrupt Controller Register Map for dsPIC33EPXXXMC806 Devices Only64TABLE 4-7: Interrupt Controller Register Map for dsPIC33EPXXXGP806 and PIC24EPXXXGP806 Devices Only66TABLE 4-8: Interrupt Controller Register Map for PIC24EPXXXGU810/814 Devices Only68TABLE 4-9: Timer1 through Timer9 Register Map70TABLE 4-10: Input Capture 1 through Input Capture 16 Register Map71TABLE 4-11: Output Compare 1 through Output Compare 16 Register Map73TABLE 4-12: PWM Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only76TABLE 4-13: PWM Generator 1 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only76TABLE 4-14: PWM Generator 2 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only77TABLE 4-15: PWM Generator 3 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only77TABLE 4-16: PWM Generator 4 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only78TABLE 4-17: PWM Generator 5 Register Map for dsPIC33EPXXX(MC/MU)810/814 Devices Only78TABLE 4-18: PWM Generator 6 Register Map for dsPIC33EPXXX(MC/MU)810/814 Devices Only79TABLE 4-19: PWM Generator 7 Register Map for dsPIC33EPXXX(MC/MU)814 Devices Only79TABLE 4-20: QEI1 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only80TABLE 4-21: QEI2 Register Map for dsPIC33EPXXX(MC/MU)806/810/814 Devices Only81TABLE 4-22: I2C1 and I2C2 Register Map82TABLE 4-23: UART1, UART2, UART3 and UART4 Register Map83TABLE 4-24: SPI1, SPI2, SPI3 and SPI4 Register Map84TABLE 4-25: ADC1 and ADC2 Register Map85TABLE 4-26: DCI Register Map87TABLE 4-27: USB OTG Register Map for dsPIC33EPMU806/810/814 and PIC24EPGU806/10/814) Devices Only88TABLE 4-28: ECAN1 Register Map When WIN (C1CTRL<0>) = 0 or 190TABLE 4-29: ECAN1 Register Map When WIN (C1CTRL<0>) = 090TABLE 4-30: ECAN1 Register Map When WIN (C1CTRL<0>) = 191TABLE 4-31: ECAN2 Register Map When WIN (C2CTRL<0>) = 0 or 193TABLE 4-32: ECAN2 Register Map When WIN (C2CTRL<0>) = 093TABLE 4-33: ECAN2 Register Map When WIN (C2CTRL<0>) = 194TABLE 4-34: Parallel Master/Slave Port Register Map96TABLE 4-35: CRC Register Map96TABLE 4-36: Real-Time Clock and Calendar Register Map96TABLE 4-37: Peripheral Pin Select Output Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only97TABLE 4-38: Peripheral Pin Select Output Register Map for dsPIC33EPXXXMU806 Devices Only98TABLE 4-39: Peripheral Pin Select Output Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only98TABLE 4-40: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMU814 Devices Only99TABLE 4-41: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMU810 Devices Only101TABLE 4-42: Peripheral Pin Select Input Register Map for dsPIC33EPXXX(MC/MU)806 Devices Only103TABLE 4-43: Peripheral Pin Select Input Register Map for PIC24EPXXXGU810/814 Devices Only105TABLE 4-44: Reference Clock Register Map106TABLE 4-45: NVM Register Map106TABLE 4-46: System Control Register Map106TABLE 4-47: PMD Register Map for dsPIC33EPXXXMU814 Devices Only107TABLE 4-48: PMD Register Map for dsPIC33EPXXXMU810 Devices Only107TABLE 4-49: PMD Register Map for dsPIC33EPXXXMU806 Devices Only108TABLE 4-50: PMD Register Map for dsPIC33EPXXXMC806 Devices Only108TABLE 4-51: PMD Register Map for dsPIC33EPXXXGP8XX and PIC24EPXXXGP8XX Devices Only109TABLE 4-52: PMD Register Map for PIC24EPXXXGU810/814 Devices Only109TABLE 4-53: Comparator Register Map110TABLE 4-54: DMAC Register Map111TABLE 4-55: PORTA Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only115TABLE 4-56: PORTB Register Map115TABLE 4-57: PORTC Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only115TABLE 4-58: PORTC Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only116TABLE 4-59: PORTD Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only116TABLE 4-60: PORTD Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only116TABLE 4-61: PORTE Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only117TABLE 4-62: PORTE Register Map for dsPIC33EPXXX(GP/MC/MU)806 and PIC24EPXXXGP806 Devices Only117TABLE 4-63: PORTF Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only117TABLE 4-64: PORTF Register Map for dsPIC33EPXXX(GP/MC)806 and PIC24EPXXXGP806 Devices Only118TABLE 4-65: PORTF Register Map for dsPIC33EPXXXMU806 Devices Only118TABLE 4-66: PORTG Register Map for dsPIC33EPXXXMU810/814 and PIC24EPXXXGU810/814 Devices Only118TABLE 4-67: PORTG Register Map for dsPIC33EPXXX(GP/MC)806 and PIC24EPXXXGP806 Devices Only119TABLE 4-68: PORTG Register Map for dsPIC33EPXXXMU806 Devices Only119TABLE 4-69: PORTH Register Map for dsPIC33EPXXXMU814 and PIC24EPXXXGU814 Devices Only120TABLE 4-70: PORTJ Register Map for dsPIC33EPXXXMU814 and PIC24EPXXXGU814 Devices Only120TABLE 4-71: PORTK Register Map for dsPIC33EPXXXMU814 and PIC24EPXXXGU814 Devices Only121TABLE 4-72: Pad Configuration Register Map1214.4.1 Paged Memory Scheme122EXAMPLE 4-1: Extended Data Space (EDS) Read Address Generation122EXAMPLE 4-2: Extended Data Space (EDS) Write Address Generation123EXAMPLE 4-3: Paged Data Memory Space124TABLE 4-73: Overflow and Underflow Scenarios at Page 0, EDS and PSV Space Boundaries(2,3,4)1254.4.2 Extended X Data Space126FIGURE 4-7: EDS Memory Map1264.4.3 EDS Arbitration and Bus Master Priority127TABLE 4-74: EDS Bus Arbiter Priority127FIGURE 4-8: EDS Arbiter Architecture1274.4.4 Software Stack128FIGURE 4-9: CALL Stack Frame1284.5 Instruction Addressing Modes1284.5.1 File Register Instructions1284.5.2 MCU Instructions128TABLE 4-75: Fundamental Addressing Modes Supported1294.5.3 Move and Accumulator Instructions1294.5.4 MAC Instructions (dsPIC33EPXXXMU806/810/814 Devices Only)1294.5.5 Other Instructions1294.6 Modulo Addressing (dsPIC33EPXXXMU806/810/814 Devices Only)1304.6.1 Start and End Address1304.6.2 W Address Register Selection130FIGURE 4-10: Modulo Addressing Operation Example1304.6.3 Modulo Addressing Applicability1314.7 Bit-Reversed Addressing (dsPIC33EPXXXMU806/810/814 Devices Only)1314.7.1 Bit-Reversed Addressing Implementation131FIGURE 4-11: Bit-Reversed Address Example132TABLE 4-76: Bit-Reversed Address Sequence (16-Entry)1324.8 Interfacing Program and Data Memory Spaces133TABLE 4-77: Program Space Address Construction133FIGURE 4-12: Data Access from Program Space Address Generation1334.8.1 Data Access From Program Memory Using Table Instructions134FIGURE 4-13: Accessing Program Memory with Table Instructions1345.0 Flash Program Memory1355.1 Table Instructions and Flash Programming135FIGURE 5-1: Addressing for Table Registers1355.2 RTSP Operation1365.3 Programming Operations136EQUATION 5-1: Programming Time136EQUATION 5-2: Minimum Row Write Time136EQUATION 5-3: Maximum Row Write Time1365.4 Flash Program Memory Resources1375.4.1 Key Resources1375.5 Control Registers137Register 5-1: NVMCON: Non-Volatile Memory (NVM) Control Register138Register 5-2: NVMADRU: NonVolatile Memory Upper Address Register139Register 5-3: NVMADR: NonVolatile Memory Address Register139Register 5-4: NVMKEY: NonVolatile Memory Key RegisteR1396.0 Resets141FIGURE 6-1: Reset System Block Diagram1416.1 Resets Resources1426.1.1 Key Resources1426.2 RCON Control Register142Register 6-1: RCON: Reset Control Register(1)1437.0 Interrupt Controller1457.1 Interrupt Vector Table1457.2 Auxiliary Interrupt Vector1457.3 Reset Sequence145FIGURE 7-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Interrupt Vector Table146TABLE 7-1: Interrupt Vector Details1477.4 Interrupt Resources1507.4.1 Key Resources1507.5 Interrupt Control and Status Registers1507.5.1 INTCON1 through INTCON41507.5.2 IFSx1507.5.3 IECx1507.5.4 IPCx1507.5.5 INTTREG1507.5.6 status/Control registers150Register 7-1: SR: CPU Status Register(1)151Register 7-2: CORCON: Core Control Register(1)152Register 7-3: INTCON1: Interrupt Control Register 1153Register 7-4: INTCON2: Interrupt Control Register 2155Register 7-5: INTCON3: Interrupt Control Register 3156Register 7-6: INTCON4: Interrupt Control Register 4156Register 7-7: INTTREG: Interrupt Control and Status Register1578.0 Direct Memory Access (DMA)159FIGURE 8-1: DMA Controller159TABLE 8-1: DMA Channel to Peripheral Associations160FIGURE 8-2: DMA Controller to Peripheral Associations Block Diagram1618.1 DMA Resources1628.1.1 Key Resources1628.2 DMA Control Registers162Register 8-1: DMAxCON: DMA Channel x Control Register163Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register164Register 8-3: DMAxSTAH: DMA Channel x Start Address Register A (High)165Register 8-4: DMAxSTAL: DMA Channel x Start Address Register A (Low)165Register 8-5: DMAxSTBH: DMA Channel x Start Address Register B (High)166Register 8-6: DMAxSTBL: DMA Channel x Start Address Register B (Low)166Register 8-7: DMAxPAD: DMA Channel x Peripheral Address Register(1)167Register 8-8: DMAxCNT: DMA Channel x Transfer Count Register(1)167Register 8-9: DSADRH: Most Recent DMA Data Space High Address Register168Register 8-10: DSADRL: Most Recent DMA Data Space Low Address Register168Register 8-11: DMAPWC: DMA Peripheral Write Collision Status Register169Register 8-12: DMARQC: DMA Request Collision Status Register171Register 8-13: DMALCA: DMA Last Channel Active Status Register173Register 8-14: DMAPPS: DMA Ping-Pong Status Register1749.0 Oscillator Configuration177FIGURE 9-1: Oscillator System Diagram1789.1 CPU Clocking System179EQUATION 9-1: Device Operating Frequency179FIGURE 9-2: PLL Block Diagram179EQUATION 9-2: Fosc Calculation179EQUATION 9-3: Fvco Calculation179FIGURE 9-3: APLL Block Diagram180EQUATION 9-4: Favco Calculation180TABLE 9-1: Configuration Bit Values for Clock Selection1819.2 Oscillator Resources1819.2.1 Key Resources1819.3 Oscillator Control Registers182Register 9-1: OSCCON: Oscillator Control Register(1,3)182Register 9-2: CLKDIV: Clock Divisor Register(2)184Register 9-3: PLLFBD: PLL Feedback Divisor Register(1)186Register 9-4: OSCTUN: FRC Oscillator Tuning Register(1)187Register 9-5: ACLKCON3: Auxiliary Clock Control Register 3(1,2)188Register 9-6: ACLKDIV3: Auxiliary Clock Divisor Register 3(1,2)189Register 9-7: REFOCON: Reference Oscillator Control Register19010.0 Power-Saving Features19110.1 Clock Frequency and Clock Switching19110.2 Instruction-Based Power-Saving Modes19110.2.1 Sleep Mode191EXAMPLE 10-1: PWRSAV Instruction Syntax19110.2.2 Idle Mode19210.2.3 Interrupts Coincident with Power Save Instructions19210.3 Doze Mode19210.4 Peripheral Module Disable19210.5 Power-Saving Resources19310.5.1 Key Resources19310.6 Special Function Registers193Register 10-1: PMD1: Peripheral Module Disable Control Register 1194Register 10-2: PMD2: Peripheral Module Disable Control Register 2196Register 10-3: PMD3: Peripheral Module Disable Control Register 3198Register 10-4: PMD4: Peripheral Module Disable Control Register 4200Register 10-5: PMD5: Peripheral Module Disable Control Register 5201Register 10-6: PMD6: Peripheral Module Disable Control Register 6203Register 10-7: PMD7: Peripheral Module Disable Control Register 720411.0 I/O Ports20711.1 Parallel I/O (PIO) Ports207FIGURE 11-1: Block Diagram of a Typical Shared Port Structure20811.1.1 Open-Drain Configuration20911.2 Configuring Analog and Digital Port Pins20911.2.1 I/O Port Write/Read Timing20911.3 Input Change Notification209EXAMPLE 11-1: Port Write/Read Example20911.4 Peripheral Pin Select21011.4.1 Available Pins21011.4.2 Available Peripherals21011.4.3 Controlling Peripheral Pin Select21011.4.4 Input Mapping210FIGURE 11-2: U1RX Remappable Input210TABLE 11-1: Selectable Input Sources (Maps Input to Function)211TABLE 11-2: Input Pin Selection for Selectable Input Sources213FIGURE 11-3: Multiplexing of Remappable Output for RPn215TABLE 11-3: Output Selection for Remappable Pins (RPn)215EXAMPLE 11-2: Connecting IC1 to HOME1 Digital Filter Input on Pin 3 of the dsPIC33EP512MU810 Device21711.5 I/O Helpful Tips21811.6 I/O Resources21911.6.1 Key Resources21911.7 Peripheral Pin Select Control Registers220Register 11-1: RPINR0: Peripheral Pin Select Input Register 0220Register 11-2: RPINR1: Peripheral Pin Select Input Register 1221Register 11-3: RPINR2: Peripheral Pin Select Input Register 2222Register 11-4: RPINR3: Peripheral Pin Select Input Register 3223Register 11-5: RPINR4: Peripheral Pin Select Input Register 4224Register 11-6: RPINR5: Peripheral Pin Select Input Register 5225Register 11-7: RPINR6: Peripheral Pin Select Input Register 6226Register 11-8: RPINR7: Peripheral Pin Select Input Register 7227Register 11-9: RPINR8: Peripheral Pin Select Input Register 8228Register 11-10: RPINR9: Peripheral Pin Select Input Register 9229Register 11-11: RPINR10: Peripheral Pin Select Input Register 10230Register 11-12: RPINR11: Peripheral Pin Select Input Register 11231Register 11-13: RPINR12: Peripheral Pin Select Input Register 12 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)232Register 11-14: RPINR13: Peripheral Pin Select Input Register 13 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)233Register 11-15: RPINR14: Peripheral Pin Select Input Register 14 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)234Register 11-16: RPINR15: Peripheral Pin Select Input Register 15 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)235Register 11-17: RPINR16: Peripheral Pin Select Input Register 16 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)236Register 11-18: RPINR17: Peripheral Pin Select Input Register 17 (dsPIC33EPXXXMU806/810/814 dEVICES oNLY)237Register 11-19: RPINR18: Peripheral Pin Select Input Register 18238Register 11-20: RPINR19: Peripheral Pin Select Input Register 19239Register 11-21: RPINR20: Peripheral Pin Select Input Register 20240Register 11-22: RPINR21: Peripheral Pin Select Input Register 21241Register 11-23: RPINR23: Peripheral Pin Select Input Register 23241Register 11-24: RPINR24: Peripheral Pin Select Input Register 24242Register 11-25: RPINR25: Peripheral Pin Select Input Register 25243Register 11-26: RPINR26: Peripheral Pin Select Input Register 26244Register 11-27: RPINR27: Peripheral Pin Select Input Register 27245Register 11-28: RPINR28: Peripheral Pin Select Input Register 28246Register 11-29: RPINR29: Peripheral Pin Select Input Register 29247Register 11-30: RPINR30: Peripheral Pin Select Input Register 30248Register 11-31: RPINR31: Peripheral Pin Select Input Register 31249Register 11-32: RPINR32: Peripheral Pin Select Input Register 32250Register 11-33: RPINR33: Peripheral Pin Select Input Register 33251Register 11-34: RPINR34: Peripheral Pin Select Input Register 34252Register 11-35: RPINR35: Peripheral Pin Select Input Register 35253Register 11-36: RPINR36: Peripheral Pin Select Input Register 36254Register 11-37: RPINR37: Peripheral Pin Select Input Register 37255Register 11-38: RPINR38: Peripheral Pin Select Input Register 38256Register 11-39: RPINR39: Peripheral Pin Select Input Register 39257Register 11-40: RPINR40: Peripheral Pin Select Input Register 40258Register 11-41: RPINR41: Peripheral Pin Select Input Register 41259Register 11-42: RPINR42: Peripheral Pin Select Input Register 42260Register 11-43: RPINR43: Peripheral Pin Select Input Register 43261Register 11-44: RPOR0: Peripheral Pin Select Output Register 0261Register 11-45: RPOR1: Peripheral Pin Select Output Register 1262Register 11-46: RPOR2: Peripheral Pin Select Output Register 2262Register 11-47: RPOR3: Peripheral Pin Select Output Register 3263Register 11-48: RPOR4: Peripheral Pin Select Output Register 4263Register 11-49: RPOR5: Peripheral Pin Select Output Register 5264Register 11-50: RPOR6: Peripheral Pin Select Output Register 6264Register 11-51: RPOR7: Peripheral Pin Select Output Register 7265Register 11-52: RPOR8: Peripheral Pin Select Output Register 8265Register 11-53: RPOR9: Peripheral Pin Select Output Register 9266Register 11-54: RPOR10: Peripheral Pin Select Output Register 10266Register 11-55: RPOR11: Peripheral Pin Select Output Register 11267Register 11-56: RPOR12: Peripheral Pin Select Output Register 12267Register 11-57: RPOR13: Peripheral Pin Select Output Register 13268Register 11-58: RPOR14: Peripheral Pin Select Output Register 14268Register 11-59: RPOR15: Peripheral Pin Select Output Register 1526912.0 Timer1271TABLE 12-1: Timer Mode Settings271FIGURE 12-1: 16-Bit Timer1 Module Block Diagram27112.1 Timer Resources27212.1.1 Key Resources27212.2 Timer1 Control Register273Register 12-1: T1CON: Timer1 Control Register27313.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9275FIGURE 13-1: Type B Timerx block Diagram (x = 2, 4, 6 and 8)276FIGURE 13-2: Type C Timerx Block Diagram (x = 3, 5, 7 and 9)276FIGURE 13-3: Type B/Type C Timer Pair Block Diagram (32-bit Timer)27713.1 Timer Resources27713.1.1 Key Resources27713.2 Timerx/y Control Registers278Register 13-1: TxCON: (T2CON, T4CON, T6CON or T8CON) Control Register278Register 13-2: TyCON: (T3CON, T5CON, T7CON or T9CON) Control Register27914.0 Input Capture281FIGURE 14-1: Input Capture Module Block Diagram28114.1 Input Capture Resources28214.1.1 Key Resources28214.2 Input Capture Control Registers283Register 14-1: ICxCON1: Input Capture X Control Register 1283Register 14-2: ICxCON2: Input Capture X Control Register 228415.0 Output Compare287FIGURE 15-1: Output Compare Module Block Diagram28715.1 Output Compare Resources28815.1.1 Key Resources28815.2 Output Compare Control Registers289Register 15-1: OCxCON1: Output Compare x Control Register 1289Register 15-2: OCxCON2: Output Compare x Control Register 229116.0 High-Speed PWM Module (dsPIC33EPXXX(MC/MU)8XX Devices Only)293FIGURE 16-1: High-Speed PWM Module Architectural Overview294FIGURE 16-2: High-Speed PWM MOdule Register Interconnection Diagram29516.1 PWM Resources29616.1.1 Key Resources29616.2 PWM Control Registers297Register 16-1: PTCON: PWM Time Base Control Register297Register 16-2: PTCON2: PWM Primary Master Clock Divider Select Register 2299Register 16-3: PTPER: Primary Master Time Base Period Register299Register 16-4: SEVTCMP: PWM Primary Special Event Compare Register300Register 16-5: STCON: PWM Secondary Master Time Base Control Register301Register 16-6: STCON2: PWM Secondary Clock Divider Select Register 2302Register 16-7: STPER: Secondary Master Time Base Period Register(1)302Register 16-8: SSEVTCMP: PWM Secondary Special Event Compare Register303Register 16-9: CHOP: PWM Chop Clock Generator Register303Register 16-10: MDC: PWM Master Duty Cycle Register304Register 16-11: PWMCONx: PWMx Control Register305Register 16-12: PDCx: PWMx Generator Duty Cycle Register(1)307Register 16-13: SDCx: PWMx Secondary Duty Cycle Register(1)307Register 16-14: PHASEx: PWMx Primary Phase Shift Register(1,2)308Register 16-15: SPHASEx: PWMx Secondary Phase Shift Register(1,2)309Register 16-16: DTRx: PWMx Dead-Time Register310Register 16-17: ALTDTRx: PWMx Alternate Dead-Time Register310Register 16-18: TRGCONx: PWMx Trigger Control Register311Register 16-19: IOCONx: PWMx I/O Control Register312Register 16-20: TRIGx: PWMx Primary Trigger Compare Value Register314Register 16-21: FCLCONx: PWMx Fault Current-Limit Control Register315Register 16-22: LEBCONx: Leading-Edge Blanking Control Register x317Register 16-23: LEBDLYx: Leading-Edge Blanking Delay Register x318Register 16-24: AUXCONx: PWM Auxiliary Control Register x319Register 16-25: PWMCAPx: Primary PWMx Time Base Capture Register32017.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXX(MC/MU)8XX Devices Only)321FIGURE 17-1: QEI Block Diagram32217.1 QEI Resources32317.1.1 Key Resources32317.2 QEI Control Registers324Register 17-1: QEIxCON: QEIx Control Register324Register 17-2: QEIxIOC: QEIx I/O Control Register326Register 17-3: QEIxSTAT: QEIx Status register328Register 17-4: POSxCNTH: Position Counter x High Word Register330Register 17-5: POSxCNTL: Position Counter x Low Word Register330Register 17-6: POSxHLD: Position Counter x Hold Register330Register 17-7: VELxCNT: Velocity Counter x Register331Register 17-8: INDXxCNTH: Index Counter x High Word Register331Register 17-9: INDXxCNTL: Index Counter x Low Word Register331Register 17-10: INDXxHLD: Index Counter x Hold Register332Register 17-11: QEIxICH: QEIx Initialization/Capture High Word Register332Register 17-12: QEIxICL: QEIx Initialization/Capture Low Word Register332Register 17-13: QEIxLECH: QEIx Less Than or Equal Compare High Word Register333Register 17-14: QEIxLECL: QEIx Less Than or Equal Compare Low Word Register333Register 17-15: QEIxGECH: QEIx Greater Than or Equal Compare High Word Register334Register 17-16: QEIxGECL: QEIx Greater Than or Equal Compare Low Word Register334Register 17-17: INTxTMRH: Interval Timer x High Word Register334Register 17-18: INTxTMRL: INterval Timer x Low Word Register335Register 17-19: INTxHLDH: Interval Timer x Hold High Word Register335Register 17-20: INTxHLDL: Interval Timer x Hold Low Word Register33518.0 Serial Peripheral Interface (SPI)337FIGURE 18-1: SPIx Module Block Diagram33718.1 SPI Helpful Tips33818.2 SPI Resources33818.2.1 Key Resources33818.3 SPI Control Registers339Register 18-1: SPIxSTAT: SPIx Status and Control Register339Register 18-2: SPIxCON1: SPIx Control Register 1341Register 18-3: SPIxCON2: SPIx Control Register 234319.0 Inter-Integrated Circuit™ (I2C™)345FIGURE 19-1: I2C™ Block Diagram (x = 1 or 2)34619.1 I2C Resources34719.1.1 Key Resources34719.2 I2C Control Registers348Register 19-1: I2CxCON: I2Cx Control Register348Register 19-2: I2CxSTAT: I2Cx Status Register350Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register35220.0 Universal Asynchronous Receiver Transmitter (UART)353FIGURE 20-1: UARTx Simplified Block Diagram35320.1 UARTx Helpful Tips35420.2 UARTx Resources35420.2.1 Key Resources35420.3 UARTx Registers355Register 20-1: UxMODE: UARTx Mode Register355Register 20-2: UxSTA: UARTx Status and Control Register35721.0 Enhanced CAN (ECAN™) Module35921.1 Overview359FIGURE 21-1: ECANx Module Block Diagram36021.2 Modes of Operation36121.3 ECAN Resources36121.3.1 Key Resources36121.4 ECANx Control Registers362Register 21-1: CxCTRL1: ECANx CONTROL REGISTER 1362Register 21-2: CxCTRL2: ECANx Control Register 2363Register 21-3: CxVEC: ECANx Interrupt Code Register364Register 21-4: CxFCTRL: ECANx FIFO Control Register365Register 21-5: CxFIFO: ECANx FIFO Status Register366Register 21-6: CxINTF: ECANx Interrupt Flag Register367Register 21-7: CxINTE: ECANx Interrupt Enable Register368Register 21-8: CxEC: ECANx Transmit/Receive Error Count Register369Register 21-9: CxCFG1: ECANx Baud Rate Configuration Register 1369Register 21-10: CxCFG2: ECANx Baud Rate Configuration Register 2370Register 21-11: CxFEN1: ECANx Acceptance Filter Enable Register 1371Register 21-12: CxBUFPNT1: ECANx Filter 0-3 Buffer Pointer Register 1371Register 21-13: CxBUFPNT2: ECANx Filter 4-7 Buffer Pointer Register 2372Register 21-14: CxBUFPNT3: ECANx Filter 8-11 Buffer Pointer Register 3372Register 21-15: CxBUFPNT4: ECANx Filter 12-15 Buffer Pointer Register 4373Register 21-16: CxRXFnSID: ECANx Acceptance Filter n Standard Identifier Register n (n = 0-15)374Register 21-17: CxRXFnEID: ECANx Acceptance Filter n Extended Identifier Register n (n = 0-15)375Register 21-18: CxFMSKSEL1: ECANx Filter 7-0 Mask Selection Register375Register 21-19: CxFMSKSEL2: ECANx Filter 15-8 Mask Selection Register376Register 21-20: CxRXMnSID: ECANx Acceptance Filter Mask n Standard Identifier Register n (n = 0-2)377Register 21-21: CxRXMnEID: ECANx Acceptance Filter Mask n Extended Identifier Register n (n = 0-2)377Register 21-22: CxRXFUL1: ECANx Receive Buffer Full Register 1378Register 21-23: CxRXFUL2: ECANx Receive Buffer Full Register 2378Register 21-24: CxRXOVF1: ECANx Receive Buffer Overflow Register 1379Register 21-25: CxRXOVF2: ECANx Receive Buffer Overflow Register 2379Register 21-26: CxTRmnCON: ECANx TX/RX Buffer m Control Register (m = 0, 2, 4, 6; n = 1, 3, 5, 7)38021.5 ECAN Message Buffers38122.0 USB On-The-Go (OTG) Module (dsPIC33EPXXXMU8XX and PIC24EPGU8XX Devices Only)38522.1 Overview38522.2 Clearing USB OTG Interrupts385FIGURE 22-1: USB Interface Diagram38622.3 USB OTG Resources38722.3.1 Key Resources38722.4 USB Control Registers388Register 22-1: UxOTGSTAT: USB OTG Status Register388Register 22-2: UxOTGCON: USB On-The-Go Control Register389Register 22-3: UxPWRC: USB Power Control Register390Register 22-4: UxSTAT: USB Status Register391Register 22-5: UxCON: USB Control Register (Device mode)392Register 22-6: UxCON: USB Control Register (Host mode)393Register 22-7: UxADDR: USB Address Register394Register 22-8: UxTOK: USB Token Register (Host mode only)394Register 22-9: UxSOF: USB OTG Start-Of-Token Threshold Register (Host mode only)395Register 22-10: UxCNFG1: USB Configuration Register 1395Register 22-11: UxCNFG2: USB Configuration Register 2396Register 22-12: UxOTGIR: USB OTG Interrupt Status Register (Host mode only)397Register 22-13: UxOTGIE: USB OTG Interrupt Enable Register (Host mode only)398Register 22-14: UxIR: USB Interrupt Status Register (Device mode only)399Register 22-15: UxIR: USB Interrupt Status Register (Host mode only)400Register 22-16: UxIE: USB Interrupt Enable Register (Device mode)401Register 22-17: UxIE: USB Interrupt Enable Register (Host mode)402Register 22-18: UxEIR: USB Error Interrupt Status Register (Device mode)403Register 22-19: UxEIR: USB Error Interrupt Status Register (Host mode)404Register 22-20: UxEIE: USB Error Interrupt Enable Register (Device mode)405Register 22-21: UxEIE: USB Error Interrupt Enable Register (Host mode)406Register 22-22: UxEPn: USB Endpoint n Control Registers (n = 0 to 15)407Register 22-23: UxBDTP1: USB Buffer Description Table Register 1408Register 22-24: UxBDTP2: USB Buffer Description Table Register 2408Register 22-25: UxBDTP3: USB Buffer Description Table Register 3409Register 22-26: UxPWMCON: USB Vbus PWM Generator Control Register409Register 22-27: UxPWMRRS: Duty Cycle and PWM Period Register410Register 22-28: UxFRMH: USB Frame Number High Register410Register 22-29: UxFRML: USB Frame Number Low Register41123.0 10-Bit/12-Bit Analog-to- Digital Converter (ADC)41323.1 Key Features413FIGURE 23-1: ADCx Module Block Diagram414FIGURE 23-2: ADCx Conversion Clock Period Block Diagram41523.2 ADC Helpful Tips41623.3 ADC Resources41623.3.1 Key Resources41623.4 ADC Control Registers417Register 23-1: ADxCON1: ADCx Control Register 1417Register 23-2: AD1CON2: ADC1 Control Register 2419Register 23-3: AD2CON2: ADC2 Control Register 2421Register 23-4: ADxCON3: ADCx Control Register 3423Register 23-5: ADxCON4: ADCx Control Register 4424Register 23-6: ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register425Register 23-7: ADxCHS0: ADCx Input Channel 0 Select Register426Register 23-8: AD1CSSH: ADC1 Input Scan Select Register High(1,2,3)427Register 23-9: ADxCSSL: ADCx Input Scan Select Register Low(1,2)42724.0 Data Converter Interface (DCI) Module42924.1 Module Introduction429FIGURE 24-1: DCI Module Block Diagram42924.2 DCI Resources43024.2.1 Key Resources43024.3 DCI Control Registers431Register 24-1: DCICON1: DCI Control Register 1431Register 24-2: DCICON2: DCI Control Register 2432Register 24-3: DCICON3: DCI Control Register 3433Register 24-4: DCISTAT: DCI Status Register434Register 24-5: RSCON: DCI Receive Slot Control Register435Register 24-6: TSCON: DCI Transmit Slot Control Register43525.0 Comparator Module437FIGURE 25-1: Comparator I/O Operating Modes437FIGURE 25-2: Comparator Voltage Reference Block Diagram438FIGURE 25-3: User-Programmable Blanking Function Block Diagram438FIGURE 25-4: Digital Filter Interconnect Block Diagram43925.1 Comparator Resources43925.1.1 Key Resources43925.2 Comparator Control Registers440Register 25-1: CMSTAT: Comparator Status Register440Register 25-2: CMxCON: Comparator x Control Register441Register 25-3: CMxMSKSRC: Comparator x Mask Source Select Control Register443Register 25-4: CMxMSKCON: Comparator x Mask Gating Control Register445Register 25-5: CMxFLTR: Comparator x Filter Control Register447Register 25-6: CVRCON: Comparator Voltage Reference Control Register44826.0 Real-Time Clock and Calendar (RTCC)449FIGURE 26-1: RTCC Block Diagram45026.1 Writing to the RTCC Timer45126.2 RTCC Resources45126.2.1 Key Resources45126.3 RTCC Registers452Register 26-1: RCFGCAL: RTCC Calibration and Configuration Register(1)452Register 26-2: PADCFG1: Pad Configuration Control Register454Register 26-3: ALCFGRPT: Alarm Configuration Register455Register 26-4: RTCVAL (when RTCPTR<1:0> = 11): YEAR VALUE Register(1)456Register 26-5: RTCVAL (when RTCPTR<1:0> = 10): MONTH AND DAY VALUE Register(1)456Register 26-6: RTCVAL (when RTCPTR<1:0> = 01): Weekday and Hours Value Register(1)457Register 26-7: RTCVAL (when RTCPTR<1:0> = 00): Minutes and Seconds Value Register457Register 26-8: ALRMVAL (when ALRMPTR<1:0> = 10): Alarm Month and Day Value Register(1)458Register 26-9: ALRMVAL (when ALRMPTR<1:0> = 01): Alarm Weekday and Hours Value Register(1)459Register 26-10: ALRMVAL (when ALRMPTR<1:0> = 00): Alarm Minutes and Seconds Value Register46027.0 Programmable Cyclic Redundancy Check (CRC) Generator461FIGURE 27-1: Programmable CRC Block Diagram461FIGURE 27-2: CRC Shift Engine Detail46127.1 Overview462TABLE 27-1: CRC SETUP EXAMPLEs FOR 16 and 32-bit polynomial46227.2 Programmable CRC Resources46227.2.1 Key Resources46227.3 Programmable CRC Registers463Register 27-1: CRCCON1: CRC Control Register 1463Register 27-2: CRCCON2: CRC Control Register 2464Register 27-3: CRCXORH: CRC XOR Polynomial HIGH Register465Register 27-4: CRCXORL: CRC XOR Polynomial Low Register46528.0 Parallel Master Port (PMP)467FIGURE 28-1: PMP Module Pinout and Connections to External Devices46728.1 PMP Resources46828.1.1 Key Resources46828.2 PMP Control Registers469Register 28-1: PMCON: Parallel Master Port Control Register469Register 28-2: PMMODE: Parallel Master Port Mode Register471Register 28-3: PMADDR: Parallel Master Port Address Register (Master modes only)(1)473Register 28-4: PMAEN: Parallel Master Port Address Enable Register474Register 28-5: PMSTAT: Parallel Master Port Status Register (Slave mode only)475Register 28-6: PADCFG1: Pad Configuration Control Register47629.0 Special Features47729.1 Configuration Bits477TABLE 29-1: Device Configuration Register Map477TABLE 29-2: Configuration Bits Description47829.2 On-Chip Voltage Regulator481FIGURE 29-1: Connections for the On-Chip Voltage Regulator(1,2,3)48129.3 Brown-out Reset (BOR)48129.4 Watchdog Timer (WDT)48229.4.1 Prescaler/Postscaler48229.4.2 Sleep and Idle Modes48229.4.3 Enabling WDT482FIGURE 29-2: WDT Block diagram48229.5 JTAG Interface48329.6 In-Circuit Serial Programming48329.7 In-Circuit Debugger48329.8 Code Protection and CodeGuard™ Security48330.0 Instruction Set Summary485TABLE 30-1: Symbols used in Opcode Descriptions486TABLE 30-2: Instruction Set Overview48831.0 Development Support49531.1 MPLAB Integrated Development Environment Software49531.2 MPLAB C Compilers for Various Device Families49631.3 HI-TECH C for Various Device Families49631.4 MPASM Assembler49631.5 MPLINK Object Linker/ MPLIB Object Librarian49631.6 MPLAB Assembler, Linker and Librarian for Various Device Families49631.7 MPLAB SIM Software Simulator49731.8 MPLAB REAL ICE In-Circuit Emulator System49731.9 MPLAB ICD 3 In-Circuit Debugger System49731.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express49731.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express49831.12 MPLAB PM3 Device Programmer49831.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits49832.0 Electrical Characteristics499Absolute Maximum Ratings49932.1 DC Characteristics500TABLE 32-1: Operating MIPS vs. Voltage500TABLE 32-2: Thermal Operating Conditions500TABLE 32-3: Thermal Packaging Characteristics500TABLE 32-4: DC Temperature and Voltage specifications501TABLE 32-5: DC Characteristics: Operating Current (Idd)502TABLE 32-6: DC Characteristics: Idle Current (iidle)503TABLE 32-7: DC Characteristics: Power-Down Current (Ipd)504TABLE 32-8: DC Characteristics: doze Current (Idoze)(1)505TABLE 32-9: DC Characteristics: I/O Pin Input Specifications506TABLE 32-10: DC Characteristics: I/O Pin Output Specifications509TABLE 32-11: Electrical Characteristics: BOR509TABLE 32-12: DC Characteristics: Program Memory510TABLE 32-13: Internal Voltage Regulator Specifications51032.2 AC Characteristics and Timing Parameters511TABLE 32-14: Temperature and Voltage Specifications – AC511FIGURE 32-1: Load Conditions for Device Timing Specifications511TABLE 32-15: Capacitive Loading Requirements on Output Pins511FIGURE 32-2: External Clock Timing512TABLE 32-16: External Clock Timing Requirements512TABLE 32-17: PLL Clock Timing Specifications513TABLE 32-18: Auxiliary PLL Clock Timing SpecificationS (dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX Devices Only)513TABLE 32-19: Internal FRC Accuracy514TABLE 32-20: Internal LPRC accuracy514FIGURE 32-3: I/O Timing Characteristics515TABLE 32-21: I/O Timing Requirements515FIGURE 32-4: Power-On Reset Timing Characteristics516FIGURE 32-5: BOR and Master Clear Reset Timing Characteristics517TABLE 32-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements517FIGURE 32-6: Timer1-Timer9 External Clock Timing Characteristics518TABLE 32-23: Timer1 External Clock Timing Requirements(1)518TABLE 32-24: Timer2, Timer4, Timer6, Timer8 (TYPe B Timer) External Clock Timing Requirements519TABLE 32-25: Timer3, Timer5, Timer7, Timer9 (Type C Timer) External Clock Timing Requirements519FIGURE 32-7: TimerQ (QEI Module) External Clock Timing Characteristics520TABLE 32-26: QEI module External Clock Timing Requirements520FIGURE 32-8: INPUT CAPTURE (ICx) TIMING Characteristics521Table 32-27: Input Capture Module (ICx) Timing Requirements521FIGURE 32-9: Output Compare Module (OCx) Timing Characteristics522TABLE 32-28: Output Compare Module (OCx) timing requirements522FIGURE 32-10: OCx/PWMx Module Timing Characteristics522TABLE 32-29: OCx/PWMx MODE Timing Requirements522FIGURE 32-11: High-Speed PWMx Module fault Timing Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)523FIGURE 32-12: High-Speed PWMx Module Timing Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)523TABLE 32-30: High-Speed PWMx Module Timing Requirements (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)523FIGURE 32-13: QEA/QEB Input Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)524TABLE 32-31: Quadrature Decoder Timing Requirements (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)524FIGURE 32-14: QEI Module Index Pulse Timing Characteristics (dsPIC33EPXXX(MC/MU)806/810/814 Devices Only)525TABLE 32-32: QEI INDEX PULSE Timing Requirements (dsPIC33EPXXX(MC/MU)MU806/810/814 Devices Only)525TABLE 32-33: SPI1, SPI3 and SPI4 Maximum Data/CLock Rate Summary526FIGURE 32-15: SPI1, SPI3 and SPI4 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS526FIGURE 32-16: SPI1, SPI3 and SPI4 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS527TABLE 32-34: SPI1, SPI3 and SPI4 Master Mode (Half-Duplex, Transmit Only) Timing Requirements527FIGURE 32-17: SPI1, SPI3 and SPI4 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS528TABLE 32-35: SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements528FIGURE 32-18: SPI1, SPI3 and SPI4 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS529TABLE 32-36: SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements529FIGURE 32-19: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS530TABLE 32-37: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements531FIGURE 32-20: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS532TABLE 32-38: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements533FIGURE 32-21: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS534TABLE 32-39: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements535FIGURE 32-22: SPI1, SPI3 and SPI4 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS536TABLE 32-40: SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements537TABLE 32-41: SPI2 Maximum Data/CLock Rate Summary538FIGURE 32-23: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS538FIGURE 32-24: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS539TABLE 32-42: SPI2 Master Mode (Half-Duplex, Transmit Only) Timing Requirements539FIGURE 32-25: SPI2 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS540TABLE 32-43: SPI2 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements540FIGURE 32-26: SPI2 MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS541TABLE 32-44: SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements541FIGURE 32-27: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS542TABLE 32-45: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements543FIGURE 32-28: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS544TABLE 32-46: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements545FIGURE 32-29: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS546TABLE 32-47: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements547FIGURE 32-30: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS548TABLE 32-48: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements549FIGURE 32-31: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)550FIGURE 32-32: I2Cx Bus Data Timing Characteristics (Master mode)550TABLE 32-49: I2Cx Bus Data Timing Requirements (Master Mode)551FIGURE 32-33: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)552FIGURE 32-34: I2Cx Bus Data Timing Characteristics (slave mode)552TABLE 32-50: I2Cx Bus Data Timing Requirements (Slave Mode)553FIGURE 32-35: ECAN™ Module I/O Timing Characteristics554TABLE 32-51: ECAN™ Module I/O Timing Requirements554FIGURE 32-36: UARTx Module I/O Timing Characteristics554TABLE 32-52: UARTx Module I/O Timing Requirements554TABLE 32-53: USB OTG Module Specifications (dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX Devices Only)555TABLE 32-54: ADC Module Specifications556TABLE 32-55: ADC Module Specifications (12-Bit Mode)557TABLE 32-56: ADC Module Specifications (10-Bit Mode)558FIGURE 32-37: ADC Conversion (12-Bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000, SSRCG = 0)559TABLE 32-57: ADC Conversion (12-Bit Mode) TiminG rEQUIREMENTS560FIGURE 32-38: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000, SSRCG = 0)561FIGURE 32-39: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010)561TABLE 32-58: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS562FIGURE 32-40: DCI Module (Multi-channel, I2S modes) Timing Characteristics563TABLE 32-59: DCI Module (Multi-channel, I2S modes) Timing Requirements564FIGURE 32-41: DCI Module (AC-link mode) Timing Characteristics565TABLE 32-60: DCI Module (AC-Link Mode) Timing Requirements566TABLE 32-61: Comparator Timing Specifications567TABLE 32-62: Comparator Module Specifications567TABLE 32-63: Comparator Reference Voltage Settling Time Specifications568TABLE 32-64: Comparator Reference Voltage Specifications568Figure 32-42: Parallel Slave Port Timing569TABLE 32-65: Parallel Slave Port Timing Specifications569FIGURE 32-43: Parallel Master Port Read Timing DiAgram570TABLE 32-66: Parallel Master Port Read Timing Requirements570FIGURE 32-44: Parallel Master Port Write Timing Diagram571TABLE 32-67: Parallel Master Port Write Timing Requirements571TABLE 32-68: DMA Module Timing Requirements57133.0 DC and AC Device Characteristics Graphs573FIGURE 33-1: Voh – 4x Driver Pins @ +85ºC573FIGURE 33-2: Voh – 8x Driver Pins @ +85ºC573FIGURE 33-3: Vol – 4x Driver Pins @ +85ºC573FIGURE 33-4: Vol – 8x Driver Pins @ +85ºC573FIGURE 33-5: Typical Ipd Current @ Vdd = 3.3V574FIGURE 33-6: Typical Idd Current – Vdd = 3.3V @ +85ºC574FIGURE 33-7: Typical Idoze Current @ Vdd = 3.3V574FIGURE 33-8: Typical Iidle Current – Vdd = 3.3V @ +85ºC574FIGURE 33-9: Typical FRC Frequency @ Vdd = 3.3V575FIGURE 33-10: Typical LPRC Frequency @ Vdd = 3.3V57534.0 Packaging Information57734.1 Package Marking Information57734.1 Package Marking Information (Continued)57834.2 Package Details579Appendix A: Revision History597Revision A (December 2009)597Revision B (July 2010)597TABLE A-1: Major Section Updates597Revision C (May 2011)601TABLE A-2: Major Section Updates601Revision D (August 2011)603TABLE A-3: Major Section Updates603Revision E (August 2011)605Revision F (February 2012)606TABLE A-4: Major Section Updates606Revision G (October 2012)607INDEX609The Microchip Web Site617Customer Change Notification Service617Customer Support617Reader Response618Product Identification System619Worldwide Sales and Service622サイズ： 4.97MBページ数： 622Language: Englishマニュアルを開く
