NEC PD78F9488 Manuale Utente
CHAPTER 9 WATCHDOG TIMER
User’s Manual U15331EJ4V1UD
169
9.3 Watchdog Timer Control Registers
The watchdog timer is controlled by the following two registers.
• Watchdog timer clock selection register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Watchdog timer clock selection register (WDCS)
• Watchdog timer clock selection register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Watchdog timer clock selection register (WDCS)
This register sets the watchdog timer count clock.
WDCS is set with an 8-bit memory manipulation instruction.
RESET input sets WDCS to 00H.
WDCS is set with an 8-bit memory manipulation instruction.
RESET input sets WDCS to 00H.
Figure 9-2. Format of Watchdog Timer Clock Selection Register
WDCS2
0
0
1
1
WDCS1
0
1
0
1
f
X
/2
4
f
X
/2
6
f
X
/2
8
f
X
/2
10
(312.5 kHz)
(78.1 kHz)
(19.5 kHz)
(4.88 kHz)
WDCS0
0
0
0
0
Setting prohibited
Other than above
Watchdog timer count clock selection
2
11
/f
X
2
13
/f
X
2
15
/f
X
2
17
/f
X
(410 s)
(1.64 ms)
(6.55 ms)
(26.2 ms)
Interval
µ
0
0
0
0
0
WDCS2
WDCS1
WDCS0
WDCS
7
6
5
4
Symbol
Address
After reset
R/W
FF42H
00H
R/W
3
2
1
0
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.