NEC PD78F9488 Manuale Utente
CHAPTER 9 WATCHDOG TIMER
172
User’s Manual U15331EJ4V1UD
9.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals
specified by a preset count value.
specified by a preset count value.
Select a count clock (or interval) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock selection
register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to
1.
1.
In interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the interval timer before executing the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval
timer mode is not set unless the RESET signal is input.
2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set.
Table 9-5. Interval Time of Interval Timer
WDCS2 WDCS1 WDCS0
Interval
At
f
X
= 5.0 MHz
0 0 0
2
11
× 1/f
X
410
µ
s
0 1 0
2
13
× 1/f
X
1.64
ms
1 0 0
2
15
× 1/f
X
6.55
ms
1 1 0
2
17
× 1/f
X
26.2
ms
f
X
: Main system clock oscillation frequency