NEC PD78F9488 Manuale Utente
CHAPTER 17 STANDBY FUNCTION
312
User’s Manual U15331EJ4V1UD
17.2.2 STOP mode
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time selection register (OSTS) elapses, and then the
operation mode is set.
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time selection register (OSTS) elapses, and then the
operation mode is set.
The operation statuses in the STOP mode are shown in the following table.
Table 17-3. Operation Statuses in STOP Mode
STOP Mode Operation Status During Main System Clock Operation
Item
Subsystem Clock Operating
Subsystem Clock Stopped
Main system clock
Oscillation stopped
Subsystem clock
×4
multiplication circuit
Operation stopped
CPU Operation
stopped
Ports (output latches)
Status before STOP mode setting retained
16-bit timer 20
Operation stopped
8-bit timer 50
Operable
Note 1
Operable
Note 2
8-bit timer 60
Operable
Note 3
8-bit timer 61
Operable
Note 3
Watch timer
Operable
Note 4
Operation
stopped
Watchdog timer
Operation stopped
Key return circuit
Operable
Serial interface 20
Operable
Note 5
Serial interface 1A0
Operable
Note 5
LCD controller/driver
Operable
Note 4
Operation
stopped
A/D converter
Operation stopped
Multiplier Operation
stopped
Remote controller
receiver
receiver
Note 6
Operable
Note 4
Operation
stopped
External interrupts
Operable
Note 7
Notes 1. Operation is enabled when either the subsystem clock or the input signal from the timer 60 (when timer
60 is operable) is selected as the count clock.
2. Operation is enabled when the input signal from timer 60 (when timer 60 is operable) is selected as the
count clock.
3. Operation is enabled when the external input clock is selected as the count clock.
4. Operation is enabled when the subsystem clock is selected.
5. Operation is enabled only for a maskable interrupt that is not masked.
6.
µ
PD789489 and 78F9489 only
7. Operation is enabled only for a maskable interrupt that is not masked.