Texas Instruments TMS320C6455 Manuale Utente
DDR2 Memory Controller Registers
4.4
SDRAM Refresh Control Register (SDRFC)
The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to:
•
Enter and Exit the self-refresh state.
•
Meet the refresh requirement of the attached DDR2 device by programming the rate at which the
DDR2 memory controller issues autorefresh commands.
DDR2 memory controller issues autorefresh commands.
The SDRFC is shown in
and described in
Figure 22. SDRAM Refresh Control Register (SDRFC)
31
30
29
16
SR
Rsvd
Reserved
R/W-
R/W-
R-0x0
0x0
0x0
15
0
REFRESH_RATE
R/W-0x753
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. SDRAM Refresh Control Register (SDRFC) Field Descriptions
Bit
Field
Value
Description
31
SR
Self-refresh bit. Writing a 1 to this bit will cause connected SDRAM devices to be place into Self
Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state.
Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state.
0
Exit self-refresh mode.
1
Enter self-refresh mode.
30-16
Reserved
Reserved. Writes to this register must keep this field at its default value.
15-0
REFRESH_RATE
Refresh rate bits. The value in this field is used to define the rate at which connected SDRAM
devices will be refreshed as follows:
devices will be refreshed as follows:
SDRAM refresh rate = DDR2CLKOUT clock rate / REFRESH_RATE
Writing a value less than 0x0100 to this field will cause it to be loaded with 2 * T_RFC value from
the SDRAM Timing 1 Register.
the SDRAM Timing 1 Register.
43
SPRU970G
–
December 2005
–
Revised June 2011
C6455/C6454 DDR2 Memory Controller
Copyright
©
2005
–
2011, Texas Instruments Incorporated