Manuali utente per Texas Instruments TMS320C6455

Sommario

• TMS320C6455/C6454 DSP DDR2 Memory Controller

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  • Table of Contents

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  • Preface

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  • 1 Introduction

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    • 1.1 Purpose of the Peripheral

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    • 1.2 Features

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    • 1.3 Functional Block Diagram

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    • 1.4 Industry Standard(s) Compliance Statement

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  • 2 Peripheral Architecture

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    • 2.1 Clock Control

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    • 2.2 Memory Map

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    • 2.3 Signal Descriptions

      11
    • 2.4 Protocol Description(s)

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      • 2.4.1 Mode Register Set (MRS and EMRS)

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      • 2.4.2 Refresh Mode

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      • 2.4.3 Activation (ACTV)

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      • 2.4.4 Deactivation (DCAB and DEAC)

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      • 2.4.5 READ Command

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      • 2.4.6 Write (WRT) Command

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    • 2.5 Memory Width, Byte Alignment, and Endianness

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    • 2.6 Address Mapping

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    • 2.7 DDR2 Memory Controller Interface

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      • 2.7.1 Command Ordering and Scheduling, Advanced Concept

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      • 2.7.2 Command Starvation

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      • 2.7.3 Possible Race Condition

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    • 2.8 Refresh Scheduling

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    • 2.9 Self-Refresh Mode

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    • 2.10 Reset Considerations

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    • 2.11 DDR2 SDRAM Memory Initialization

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      • 2.11.1 DDR2 SDRAM Device Mode Register Configuration Values

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      • 2.11.2 DDR2 SDRAM Initialization After Reset

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      • 2.11.3 DDR2 SDRAM Initialization After Register Configuration

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    • 2.12 Interrupt Support

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    • 2.13 EDMA Event Support

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    • 2.14 Emulation Considerations

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  • 3 Using the DDR2 Memory Controller

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    • 3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM

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    • 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications

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      • 3.2.1 Programming the SDRAM Configuration Register (SDCFG)

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      • 3.2.2 Programming the SDRAM Refresh Control Register (SDRFC)

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      • 3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)

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      • 3.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL)

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  • 4 DDR2 Memory Controller Registers

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    • 4.1 Module ID and Revision Register (MIDR)

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    • 4.2 DDR2 Memory Controller Status Register (DMCSTAT)

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    • 4.3 SDRAM Configuration Register (SDCFG)

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    • 4.4 SDRAM Refresh Control Register (SDRFC)

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    • 4.5 SDRAM Timing 1 Register (SDTIM1)

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    • 4.6 SDRAM Timing 2 Register (SDTIM2)

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    • 4.7 Burst Priority Register (BPRIO)

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    • 4.8 DDR2 Memory Controller Control Register (DMCCTL)

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• Revision History

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