Fujitsu FR81S Manuale Utente
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
85
Bit name
Function
bit3 ORE:
Overrun error flag bit
"0" Read: No overrun error
"1" Read: There is an overrun error
⋅
If an overrun error occurs while a reception is in progress, this bit will be
set to "1". To clear this bit, write "1" to the REC bit of the serial status
register (SSR).
⋅
When the ORE bit and RIE bit are set to "1", a reception interrupt
request will be output.
⋅
If this flag is set, data contained in the receive data register (RDR)
becomes invalid.
⋅
When this flag is set while using the reception FIFO, the reception FIFO
enable bit will be cleared. As a result, the reception data will not be
stored in the reception FIFO.
bit2 RDRF:
Reception data full flag bit
"0" Read: Receive data register (RDR) is empty
"1" Read: Receive data register (RDR) contains data.
⋅
The flag indicates the state of the receive data register (RDR).
⋅
When received data is loaded in RDR, this flag will be set to "1" and
when RDR is read out, it will be cleared to "0".
⋅
When the RDRF bit and RIE bit are set to "1", a reception interrupt
request will be output.
⋅
While using reception FIFO, the RDRF will be set to "1" once the
reception FIFO has received the specified number of data sets.
⋅
While using reception FIFO, the bit will be cleared to "0" once the
reception FIFO becomes empty.
bit1 TDRE:
Transmission data empty
flag bit
"0" Read: Transmit data register (TDR) contains data.
"1" Read: Transmit data register (TDR) is empty
⋅
The flag indicates the state of the transmit data register (TDR).
⋅
When a transmit data is written to TDR, this flag turns to "0", which
indicates that a valid data exists in the TDR. Once a transmission starts
after data being loaded to the transmit shift register, the bit will be set to
"1", which indicates that the TDR does not contain any valid data.
⋅
When the TDRE bit and the TIE bit are set to "1", a transmission
interrupt request will be output.
⋅
When you set UPCL bit of the serial control register (SCR) to "1", the
TDRE bit will be set to "1".
⋅
For details of the timing of setting/resetting the TDRE bit while using
transmission FIFO, see Section "7.1.5 Interrupts When Using
Transmission FIFO and Flag Setting Timing".
bit0 TBI:
Transmission bus idle flag
bit
"0" Read: Transmitting
"1" Read: No transmission operation
⋅
This bit indicates that LIN-UART has no transmission in progress.
⋅
When transmission data has been written to the transmit data register
(TDR), this bit will become "0".
⋅
If the LIN Break field is set (LBR=1), this bit will be cleared to "0".
⋅
When the transmit data register (TDR) is empty (TDRE=1) and no
transmission is in progress, this bit will be set to "1".
⋅
If the LIN Break field transmission has ended, and the transmit data
register is empty, this bit will be set to "1".
⋅
When this bit is "1" and transmission bus idle interrupts are enabled
(SCR:TBIE=1), a transmission interrupt request will be output.
MB91520 Series
MN705-00010-1v0-E
1398