Fujitsu FR81S Manuale Utente
CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
5.3.4. Irregular Reset
The irregular reset is shown.
If a reset is issued without confirming the completion of reset request processing, it will generate an irregular
reset.
Once an irregular reset is generated, the following processing will be executed.
⋅
Regardless of the type of reset factor, initialize reset (INIT) will be issued.
⋅
Set the bit7: IRRST bit of RSTRR register to "1".
When an irregular reset occurs, there is no guarantee that memory contents were not destroyed by the reset
since a bus access may have been executed at the time of inputting the reset. The irregular reset does not
necessarily mean that the memory contents were destroyed, but how the bus access was executed cannot be
identified.
MB91520 Series
MN705-00010-1v0-E
286