Fujitsu FR81S Manuale Utente
CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
5.4.1. Super Initialize Reset (SINIT)
The super initialize reset (SINIT) is shown
.
The super initialize reset (SINIT) will be issued first for power-on reset, internal low-voltage detection, or
simultaneous assert of RSTX and NMIX.
This reset is exclusively used for initializing the indefinite state of division circuits and so on.
While this reset is being issued, all clocks become inactive.
When this reset is issued, an initialize reset (INIT) and a reset (RST) will be always issued at the same time.
This reset initializes the clock control register.
This reset involves the wait time of main clock oscillation to be stabilized. Along with the control register
initialization, the oscillation stabilization wait time is 2
15
× main clock cycle.
Table 5-1 Oscillation Stabilization Wait Time (SINIT)
Type
Main clock oscillation stabilization wait time
Power-on reset
2
15
× Main clock cycle
Internal low-voltage detection
2
15
× Main clock cycle
Simultaneous assert of RSTX and NMIX
2
15
× Main clock cycle
Note:
The oscillation stabilization wait time shown in the above table does not include the regulator stabilization
wait time and FLASH stabilization wait time associated with the power-on and voltage restore. These
stabilization wait time (300μs to 1200μs and maximum 80μs) are needed at power-on reset.
Figure 5-1
Oscillation Stabilization Wait Time for Power-on Reset
Oscillation
stabilization
wait time
Step-down circuit
300 to 1200μs
(PCLK× (1046+3) cycles)
Max.80μs
circuit stabilization
wait time
wait time
stabilization wait
time
time
OCDU chip reset
sequence
sequence
CPU operation
CLK
Vcc
2
15
× main
clock period
Flash step-down
MB91520 Series
MN705-00010-1v0-E
288