Emerson 752I Manuale Utente
Local PCI Bus:
PCI Bus Control Signals
8-3
ACK64*, REQ64*:
These sustained three-state output signals tell a 64-bit PCI device whether to use the 64-bit
or the 32-bit data width. Since the Katana
or the 32-bit data width. Since the Katana
752i is a 32-bit board, these signals are tied off
to indicate the 32-bit data width.
AD00-AD31:
ADDRESS and DATA bus (bits 0-31). These three-state lines are used for both address and
data handling. A bus transaction consists of an address phase followed by one or more data
phases.
data handling. A bus transaction consists of an address phase followed by one or more data
phases.
C/BE0*-C/BE3*:
BUS COMMAND and BYTE ENABLES. These three-state lines have different functions
depending on the phase of a transaction. During the address phase of a transaction these
lines define the bus command. During a data phase the lines are used as byte enables.
depending on the phase of a transaction. During the address phase of a transaction these
lines define the bus command. During a data phase the lines are used as byte enables.
CLK:
CLOCK. This is an input signal that provides timing for PCI transactions. (This is unused,
since the Katana
since the Katana
752i generates its own PCI clock signal.)
DEVSEL*:
DEVICE SELECT. This sustained three-state signal indicates when a device on the bus has
been selected as the target of the current access.
been selected as the target of the current access.
EREADY:
READY. This signal is an input for Monarch devices and an output for non-Monarch devices.
It indicates that all modules are initialized and the PCI bus is ready to be enumerated.
It indicates that all modules are initialized and the PCI bus is ready to be enumerated.
FRAME*:
CYCLE FRAME. This sustained three-state line is driven by the current master to indicate the
beginning of an access, and continues to be asserted until transaction reaches its final data
phase.
beginning of an access, and continues to be asserted until transaction reaches its final data
phase.
GNT*:
GRANT. This input signal indicates that access to the bus has been granted to a particular
master. Each master has its own GNT*.
master. Each master has its own GNT*.
IDSEL:
INITIALIZATION DEVICE SELECT. This input signal acts as a chip select during configuration
read and write transactions.
read and write transactions.
INTA*, INTB*, INTC*, INTD*:
PMC INTERRUPTS A, B, C, D. These interrupt lines are used by PCI devices to interrupt the
host processor.
host processor.
IRDY*:
INITIATOR READY. This sustained three-state signal indicates that the bus master is ready
to complete the data phase of the transaction.
to complete the data phase of the transaction.
M66EN:
ENABLE 66 MHZ. When grounded, this signal prevents 66 MHz operation of the PCI bus.
MONARCH*:
MONARCH. When this signal is grounded, it indicates that the Katana
752i baseboard is a
Monarch and must provide PCI bus enumeration and interrupt handling.
LOCK*:
LOCK. This sustained three-state signal indicates that an automatic operation may require
multiple transactions to complete. (The Katana
multiple transactions to complete. (The Katana
752i does not support this signal.)