Texas Instruments TMS320C64x DSP Manuale Utente
Video Display Registers
4-63
Video Display Port
SPRU629
Figure 4–43. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
31
28
27
16
Reserved
VBLNKYSTART1
R-0
R/W-0
15
12
11
0
Reserved
VBLNKXSTART1
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–10. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
Field Descriptions
Description
Bit
field
†
symval
†
Value
BT.656 and Y/C Mode
Raw Data Mode
31–28
Reserved
–
0
Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
0. A value written to this field has no effect.
27–16
VBLNKYSTART1
OF(value)
0–FFFh
Specifies the line (in
FLCOUNT) where
VBLNK active edge
occurs for field 1. Does
not affect EAV/SAV V bit
operation.
FLCOUNT) where
VBLNK active edge
occurs for field 1. Does
not affect EAV/SAV V bit
operation.
Specifies the line (in
FLCOUNT) where vertical
blanking begins (VBLNK
active edge) for field 1.
FLCOUNT) where vertical
blanking begins (VBLNK
active edge) for field 1.
15–12
Reserved
–
0
Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
0. A value written to this field has no effect.
11–0
VBLNKXSTART1
OF(value)
0–FFFh
Specifies the pixel (in
FPCOUNT) where
VBLNK active edge
occurs for field 1.
FPCOUNT) where
VBLNK active edge
occurs for field 1.
Specifies the pixel (in
FPCOUNT) where
vertical blanking begins
(VBLNK active edge) for
field 1.
FPCOUNT) where
vertical blanking begins
(VBLNK active edge) for
field 1.
† For CSL implementation, use the notation VP_VDVBLKS1_field_symval