Texas Instruments TMS320C3x Manuale Utente

Interrupts

7-33

Program Flow Control

Figure 7–5. IF Register Modification

Correct

Incorrect

LDI @MASK, R0

LDI IF, R1

AND R0, IF

AND @MASK, R1

LDI R1, IF

If a load of the IF register occurs simultaneously with a set or reset of a flag
by an interrupt pulse, the loading of the flag has higher priority and overwrites
the IF register value.

The ’C3x allows the CPU and DMA coprocessor to respond to and process
interrupts in parallel. Figure 7–6 on page 7-34 shows interrupt processing
flow; for the exact sequence, see Table 7–8 on page 7-36.

For a CPU interrupt to occur, at least two conditions must be met:

-

All interrupts must be enabled globally by setting the GIE bit to 0 in the status
register.

-

The interrupt must be enabled by setting the corresponding bit in the
IF register.

In the CPU interrupt processing cycle (left side of Figure 7–6), the corresponding
interrupt flag in the IF register is cleared, and interrupts are globally disabled
(GIE = 0). The CPU completes all fetched instructions. The current PC is pushed
to the top of the stack. The interrupt vector is then fetched and loaded into the
PC, and the CPU starts executing the first instruction in the interrupt service
routine (ISR).