Texas Instruments TMS320C3x Manuale Utente

Serial Ports

 

12-26

Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued)

0

Transmit clock source

Specifies the source of the transmit timer clock.

When XCLKSRC = 1, an internal clock with frequency equal
to one-half the CLKOUT frequency is used to increment the
counter.

When XCLKSRC = 0, you can use an external signal from
the CLKX pin to increment the counter.

The external clock source is synchronized internally, thus
allowing for external asynchronous clock sources that do
not exceed the specified maximum allowable external clock
frequency, that is, less than f(H1)/2.6.

0

Transmit timer status

Indicates the status of the transmit timer. It tracks what
would be the output of the uninverted CLKX pin.

This flag sets a CPU interrupt on a transition from 0 to 1. A
write has no effect.

0

Receive timer counter
restart

Resets and starts the receive timer counter.

When RGO is set to 1 and the timer is not held, the counter
is zeroed and begins incrementing on the next rising edge
of the timer input clock.

The RGO bit is cleared on the same rising edge. Writing 0
to RGO has no effect on the receive timer.

0

Receive counter hold
signal

If RHLD = 0, the counter is disabled and held in its current
state.

If RHLD = 1, the internal divide-by-2 counter is also held so
that the counter will continue where it left off.

You can read and modify the timer registers while the timer
is being held. RESET has priority over RHLD.

0

Rclock/pulse mode
control

When RC/P = 1, the clock mode is chosen. The signaling of
the status flag and external output has a 50% duty cycle.

When RC/P = 0, the status flag and external output are active
for one CLKOUT cycle during each timer period.