Motorola MC68VZ328 Manuale Utente
4-4
MC68VZ328 User’s Manual
Detailed CGM Clock Descriptions
4.3
Detailed CGM Clock Descriptions
Section 4.3.1, “CLK32 Clock Signal,” and Section 4.3.2, “PLLCLK Clock Signal,” describe in detail the
operation of each clock signal produced by the CGM.
operation of each clock signal produced by the CGM.
4.3.1
CLK32 Clock Signal
The low-frequency output of the XTAL oscillator (CLK32) is available within a few hundred milliseconds
after initial power is applied to the circuit. The frequency of the CLK32 signal is determined by the
frequency of the external crystal. The CGM supports either a 32.768 kHz or a 38.4 kHz crystal.
after initial power is applied to the circuit. The frequency of the CLK32 signal is determined by the
frequency of the external crystal. The CGM supports either a 32.768 kHz or a 38.4 kHz crystal.
NOTE:
Regardless of the crystal frequency used, the output is always labeled
CLK32.
CLK32.
Figure 4-2 represents a suggestion of how a crystal may be connected to the MC68VZ328. The values of
C1 and C2 in Figure 4-2 are determined by using the crystal load capacitance (CL), PCB stray capacitance,
Cstray (measured or approximated), and DragonBall input capacitance (Cdbvz << 1.0 pf) according to the
following formula:
C1 and C2 in Figure 4-2 are determined by using the crystal load capacitance (CL), PCB stray capacitance,
Cstray (measured or approximated), and DragonBall input capacitance (Cdbvz << 1.0 pf) according to the
following formula:
CL = Cstray + Cdbvz + (C1 * C2) / (C1 + C2)
Eqn. 4-1
Typical design values are C1 = C2 = 20 pf. The user should consult the crystal manufacturer for
appropriate circuit layout and circuit values.
appropriate circuit layout and circuit values.
The CLK32 clock signal is unique in that while the other clock sources are disabled when the MC68VZ328
is placed in sleep mode, the CLK32 clock is available as long as power is applied. See Section 4.5.1.4,
“Sleep Mode,” for detailed information on sleep mode.
is placed in sleep mode, the CLK32 clock is available as long as power is applied. See Section 4.5.1.4,
“Sleep Mode,” for detailed information on sleep mode.
Figure 4-2. Example of External Crystal Connection
4.3.2
PLLCLK Clock Signal
The PLL output frequency, PLL clock (PLLCLK), is determined by a combination of the CLK32 signal’s
input frequency and the values in the PC and QC fields of the PLLFSR. Section 4.3.2.2, “PLL Frequency
Selection,” describes the procedure for frequency selection.
input frequency and the values in the PC and QC fields of the PLLFSR. Section 4.3.2.2, “PLL Frequency
Selection,” describes the procedure for frequency selection.
EXTAL
C2*
Crystal
32.768 kHz or
38.4 kHz
XTAL
MC68VZ328
C1*
*See Equation 4-1 for design values.