Motorola MC68VZ328 Manuale Utente
Detailed CGM Clock Descriptions
Clock Generation Module and Power Control Module
4-5
4.3.2.1
PLLCLK Initial Power-up Sequence
Refer to Figure 4-3 for a graphical representation of the following power-up sequence description. When
power is initially applied to the MC68VZ328, the XTAL oscillator begins to oscillate. Due to the
low-power design on the oscillator pads, the RESET signal must be asserted (low) for at least 1.2 s to
ensure that the crystal oscillator starts and stabilizes. This is a significant change from the 250 ms required
with the previous DragonBall and DragonBall EZ processors. The length of the delay (1.2 s) is an
approximate value and should only be used as a starting point. The RESET pin (input) is a Schmitt trigger
device with a threshold of 1.4 V high and 1.0 V low.
power is initially applied to the MC68VZ328, the XTAL oscillator begins to oscillate. Due to the
low-power design on the oscillator pads, the RESET signal must be asserted (low) for at least 1.2 s to
ensure that the crystal oscillator starts and stabilizes. This is a significant change from the 250 ms required
with the previous DragonBall and DragonBall EZ processors. The length of the delay (1.2 s) is an
approximate value and should only be used as a starting point. The RESET pin (input) is a Schmitt trigger
device with a threshold of 1.4 V high and 1.0 V low.
NOTE:
On power up, the RESET signal should be deasserted after the crystal has
energized and its output has stabilized, as shown in Figure 4-3. While most
crystal oscillators typically operate with a value of 1.2 seconds, the
optimum value will be determined experimentally. Due to the inherent
nature of crystals, refer to manufacturers documentation for optimum
circuit design information.
energized and its output has stabilized, as shown in Figure 4-3. While most
crystal oscillators typically operate with a value of 1.2 seconds, the
optimum value will be determined experimentally. Due to the inherent
nature of crystals, refer to manufacturers documentation for optimum
circuit design information.
After RESET is deasserted, the PLLCLK signal is available to the divider chain, resulting in the
availability of DMACLK from prescaler 2.
availability of DMACLK from prescaler 2.
Figure 4-3. Initial Power-up Sequence Timing
VDD
XTAL OSC
RESET
DMACLK
1.2 s