Motorola MC68VZ328 Manuale Utente
Detailed CGM Clock Descriptions
Clock Generation Module and Power Control Module
4-7
Example 4-1. Configuring the PLLCLK Frequency
NEWFREQ equ somevalue
;P and Q value of new frequency
PLLCONTROL equ $FFFFF200
;PLL Control Register
PLLFREQ equ $FFFFF202
;PLL Frequency Control Register
TCOMPARE equ $FFFFF604
;Timer Compare Value Register
TCONTROL equ $FFFFF600
;Timer Control Register
IMR equ $FFFFF304
;Interrupt Mask Register
move.l IMR,-(SP)
;save the Interrupt Mask register
move.l #$fffffffd,IMR
;enable ONLY Timer interrupt
move.w #$0001,TCOMPARE
;set compare value to 2
move.w #$0119,TCONTROL
;enable Timer 2 with CLK32 source
SYNC1
btst.b #$7,PLLFREQ
;synchronize to CLK32 high level
beq.s SYNC1
;CLK32 is still not high, go back
SYNC2
btst.b #$7,PLLFREQ
;synchronize to CLK32 low level
bne.s SYNC2
;CLK32 is still not low, go back
move.w #NEWFREQ,PLLFREQ
;load the new frequency
ori.b #$8,PLLCONTROL+1
;disable the PLL (in 30 clocks)-sleep mode
stop #$2000
;stop, enable all interrupts
; the PLL shuts down here and waits for the Timer interrupt
; interrupt service for Timer occurs here
; interrupt service for Timer occurs here
move.w (SP)+,IMR
;restore the Interrupt Mask Register
rts
;PLL is now at the new frequency
; The PLL has reacquired lock and SYSCLK is stable
4.3.2.4
Programming Considerations When Changing Frequencies
The following information is provided to assist the user in programming the MC68VZ328.
•
When programming the SYSCLK frequency, ensure that it does not exceed 33.161216 MHz at any
time.
time.
•
Since the PRESC1 and PRESC2 bits are set to %1 by default, the DMACLK output is
approximately 16 MHz.
approximately 16 MHz.
•
Because most of the modules—such as the UART, SPI, general-purpose timers, and PWM—use the
SYSCLK for bit-rate generation, changing the PLLCLK frequency will also change SYSCLK and
overall system timing (except for CLK32). Therefore, once a PLLCLK frequency is selected, it
should not be changed during system operation.
SYSCLK for bit-rate generation, changing the PLLCLK frequency will also change SYSCLK and
overall system timing (except for CLK32). Therefore, once a PLLCLK frequency is selected, it
should not be changed during system operation.
•
To reduce power consumption, the output of the PLL can be disabled using the DISPLL bit in the
PLL control register, which places the chip in sleep mode. See Section 4.5.1.4, “Sleep Mode,” for
more details. When the MC68VZ328 is awakened from sleep mode by a wake-up event, the PLL
output (PLLCLK) is available after a delay determined by the setting in the WKSEL field of
PLLCR. Unlike the initial power-up sequence, the crystal oscillator is already on, so the crystal
startup time is not a factor.
PLL control register, which places the chip in sleep mode. See Section 4.5.1.4, “Sleep Mode,” for
more details. When the MC68VZ328 is awakened from sleep mode by a wake-up event, the PLL
output (PLLCLK) is available after a delay determined by the setting in the WKSEL field of
PLLCR. Unlike the initial power-up sequence, the crystal oscillator is already on, so the crystal
startup time is not a factor.