ARM R4F Manuale Utente

ARM DDI 0363E

8-15

ID013010

If a TCM interface has been built with parity error checking, you can enable this by setting the 
appropriate bits in the Auxiliary Control Register. See c1, Auxiliary Control Register on 
page 4-38. If the BTCM interface has been built with two ports, parity checking can be enabled 
for each port individually. You can pin-configure the processor to set the enable bits and 
therefore enable parity checking on reset, by tying off the PARECCENRAM input as required.

Parity bits for the data are generated on all TCM writes, regardless of whether or not the parity 
bits are being checked on reads. When a parity error is detected on a TCM read, a precise abort 
is generated. The type of the abort is shown in the appropriate Fault Status Register (FSR) as 
being a precise parity error. The processor cannot correct parity errors in the TCM.

When you use the parity error detection scheme, the PARLVRAM input to the processor selects 
between odd and even parity.

If a TCM interface has been built with either 32-bit or 64-bit ECC error checking, you can 
enable this by setting the appropriate bits in the Auxiliary Control Register. See c1, Auxiliary 
Control Register on page 4-38. On the BTCM interface, ECC checking can only be enabled for 
both ports or neither port. You can pin-configure the processor to set the enable bits and 
therefore enable ECC checking on reset, by tying off the PARECCENRAM input as required.

When a fatal error, that is, a 2-bit ECC error, is detected on a TCM read, an error is generated. 
Instruction and data reads generate the appropriate type of precise abort, and the AXI-slave 
interface returns a SLVERR response to the AXI system.

When a correctable error, that is, a 1-bit ECC error, is detected on a TCM read made by the 
AXI-slave interface, the processor corrects the data inline before returning to the system.

When a correctable ECC error is detected on a TCM read made by the instruction-side or 
data-side, the processor normally generates the correct data and writes it back to the TCM. In 
the meantime, the processor retries the read to fetch the correct instruction or data. By setting 
the appropriate bits in the Secondary Auxiliary Control Register, you can disable this behavior. 
See c15, Secondary Auxiliary Control Register on page 4-41. Instead of correcting the error in 
the TCM, the processor generates the appropriate type of precise abort.

All ECC code generation and ECC checking must be performed on a complete data chunk, 
either 32-bits or 64-bits depending on the configuration. If a read access smaller than the data 
chunk is required, the whole chunk is read. If a write smaller than the data chunk is required, the 
processor must perform read-modify-write to generate the correct data and ECC code, but it 
only does this when ECC error checking is enabled. The data read as part of the 
read-modify-write sequence is checked for ECC errors, and the errors are handled in the same 
way as for any other TCM read. The ECC code is generated and written to the TCM for every 
write, regardless of whether error checking is enabled or not, but the code is only correct if the 
write was of a complete data chunk or if the processor performed read-modify-write to generate 
the complete data chunk. All data and instruction aborts generated by the ECC logic are 
indicated in the appropriate FSR as being a precise parity error.

Each TCM port receives requests from the LSU, PFU, and AXI slave. In most cases, the LSU 
has the highest priority, followed by the PFU, with the AXI slave having lowest priority. 

When a higher-priority device is accessing a TCM port, an access from a lower-priority device 
must stall.