Manuali utente per ARM R4F

Sommario

• Cortex-R4 and Cortex-R4F Technical Reference Manual

  1
• Contents

  3
• List of Tables

  7
• List of Figures

  13
• Preface

  16
  • About this book

    17
    • Product revision status

      17
    • Intended audience

      17
    • Using this book

      17
    • Conventions

      18
    • Further reading

      20
  • Feedback

    21
    • Feedback on this product

      21
    • Feedback on this book

      21
• Introduction

  22
  • 1.1 About the processor

    23
  • 1.2 About the architecture

    24
  • 1.3 Components of the processor

    25
    • 1.3.1 Data Processing Unit

      26
    • 1.3.2 Load/store unit

      26
    • 1.3.3 Prefetch unit

      26
    • 1.3.4 L1 memory system

      26
    • 1.3.5 L2 AXI interfaces

      28
    • 1.3.6 Debug

      29
    • 1.3.7 System control coprocessor

      30
    • 1.3.8 Interrupt handling

      30
  • 1.4 External interfaces of the processor

    32
    • 1.4.1 APB Debug interface

      32
    • 1.4.2 ETM interface

      32
    • 1.4.3 Test interface

      32
  • 1.5 Power management

    33
  • 1.6 Configurable options

    34
  • 1.7 Execution pipeline stages

    38
  • 1.8 Redundant core comparison

    40
  • 1.9 Test features

    41
  • 1.10 Product documentation, design flow, and architecture

    42
    • 1.10.1 Documentation

      42
    • 1.10.2 Design flow

      42
    • 1.10.3 Architectural information

      43
  • 1.11 Product revision information

    45
    • 1.11.1 Processor identification

      45
    • 1.11.2 Architectural information

      46
• Programmer’s Model

  47
  • 2.1 About the programmer’s model

    48
  • 2.2 Instruction set states

    49
    • 2.2.1 Switching state

      49
    • 2.2.2 Interworking ARM and Thumb state

      49
  • 2.3 Operating modes

    50
  • 2.4 Data types

    51
  • 2.5 Memory formats

    52
    • 2.5.1 Byte-invariant big-endian format

      52
    • 2.5.2 Little-endian format

      52
  • 2.6 Registers

    53
    • 2.6.1 The register set

      53
  • 2.7 Program status registers

    56
    • 2.7.1 The N, Z, C, and V bits

      56
    • 2.7.2 The Q bit

      57
    • 2.7.3 The IT bits

      57
    • 2.7.4 The J bit

      58
    • 2.7.5 The DNM bits

      58
    • 2.7.6 The GE bits

      58
    • 2.7.7 The E bit

      59
    • 2.7.8 The A bit

      59
    • 2.7.9 The I and F bits

      59
    • 2.7.10 The T bit

      59
    • 2.7.11 The M bits

      60
    • 2.7.12 Modification of PSR bits by MSR instructions

      60
  • 2.8 Exceptions

    62
    • 2.8.1 Exception entry and exit summary

      62
    • 2.8.2 Reset

      64
    • 2.8.3 Interrupts

      64
    • 2.8.4 Aborts

      68
    • 2.8.5 Supervisor call instruction

      70
    • 2.8.6 Undefined instruction

      71
    • 2.8.7 Breakpoint instruction

      71
    • 2.8.8 Exception vectors

      72
  • 2.9 Acceleration of execution environments

    73
  • 2.10 Unaligned and mixed-endian data access support

    74
  • 2.11 Big-endian instruction support

    75
• Processor Initialization, Resets, and Clocking

  76
  • 3.1 Initialization

    77
    • 3.1.1 MPU

      77
    • 3.1.2 CRS

      77
    • 3.1.3 FPU

      77
    • 3.1.4 Caches

      78
    • 3.1.5 TCM

      78
  • 3.2 Resets

    81
  • 3.3 Reset modes

    82
    • 3.3.1 Power-on reset

      82
    • 3.3.2 Processor reset

      83
    • 3.3.3 Normal operation

      83
    • 3.3.4 Halt operation

      83
  • 3.4 Clocking

    84
    • 3.4.1 AXI interface clocking

      84
    • 3.4.2 Clock gating

      84
• System Control Coprocessor

  85
  • 4.1 About the system control coprocessor

    86
    • 4.1.1 System control coprocessor functional groups

      86
    • 4.1.2 System control and configuration

      88
    • 4.1.3 MPU control and configuration

      89
    • 4.1.4 Cache control and configuration

      89
    • 4.1.5 TCM control and configuration

      90
    • 4.1.6 System performance monitor

      90
    • 4.1.7 System validation

      91
  • 4.2 System control coprocessor registers

    93
    • 4.2.1 Register allocation

      93
    • 4.2.2 c0, Main ID Register

      98
    • 4.2.3 c0, Cache Type Register

      99
    • 4.2.4 c0, TCM Type Register

      100
    • 4.2.5 c0, MPU Type Register

      101
    • 4.2.6 c0, Multiprocessor ID Register

      102
    • 4.2.7 The Processor Feature Registers

      102
    • 4.2.8 c0, Debug Feature Register 0

      104
    • 4.2.9 c0, Auxiliary Feature Register 0

      105
    • 4.2.10 Memory Model Feature Registers

      105
    • 4.2.11 Instruction Set Attributes Registers

      110
    • 4.2.12 c0, Current Cache Size Identification Register

      116
    • 4.2.13 c0, Current Cache Level ID Register

      118
    • 4.2.14 c0, Cache Size Selection Register

      119
    • 4.2.15 c1, System Control Register

      119
    • 4.2.16 Auxiliary Control Registers

      122
    • 4.2.17 c1, Coprocessor Access Register

      128
    • 4.2.18 Fault Status and Address Registers

      129
    • 4.2.19 c6, MPU memory region programming registers

      133
    • 4.2.20 Cache operations

      138
    • 4.2.21 c9, BTCM Region Register

      141
    • 4.2.22 c9, ATCM Region Register

      142
    • 4.2.23 c9, TCM Selection Register

      143
    • 4.2.24 c11, Slave Port Control Register

      143
    • 4.2.25 c13, FCSE PID Register

      144
    • 4.2.26 c13, Context ID Register

      144
    • 4.2.27 c13, Thread and Process ID Registers

      145
    • 4.2.28 Validation Registers

      146
    • 4.2.29 Correctable Fault Location Register

      154
    • 4.2.30 Build Options Registers

      156
• Prefetch Unit

  160
  • 5.1 About the prefetch unit

    161
  • 5.2 Branch prediction

    162
    • 5.2.1 Disabling program flow prediction

      162
    • 5.2.2 Branch predictor

      163
    • 5.2.3 Incorrect predictions and correction

      163
  • 5.3 Return stack

    164
• Events and Performance Monitor

  165
  • 6.1 About the events

    166
  • 6.2 About the PMU

    170
  • 6.3 Performance monitoring registers

    171
    • 6.3.1 c9, Performance Monitor Control Register

      171
    • 6.3.2 c9, Count Enable Set Register

      172
    • 6.3.3 c9, Count Enable Clear Register

      173
    • 6.3.4 c9, Overflow Flag Status Register

      174
    • 6.3.5 c9, Software Increment Register

      175
    • 6.3.6 c9, Performance Counter Selection Register

      176
    • 6.3.7 c9, Cycle Count Register

      177
    • 6.3.8 c9, Event Selection Register

      177
    • 6.3.9 c9, Performance Monitor Count Registers

      179
    • 6.3.10 c9, User Enable Register

      179
    • 6.3.11 c9, Interrupt Enable Set Register

      180
    • 6.3.12 c9, Interrupt Enable Clear Register

      181
  • 6.4 Event bus interface

    183
    • 6.4.1 Use of the event bus and counters

      183
• Memory Protection Unit

  184
  • 7.1 About the MPU

    185
    • 7.1.1 Memory regions

      186
    • 7.1.2 Overlapping regions

      187
    • 7.1.3 Background regions

      189
    • 7.1.4 TCM regions

      189
  • 7.2 Memory types

    190
    • 7.2.1 Using memory types

      190
  • 7.3 Region attributes

    192
    • 7.3.1 Cacheable memory policies

      193
  • 7.4 MPU interaction with memory system

    194
  • 7.5 MPU faults

    195
    • 7.5.1 Background fault

      195
    • 7.5.2 Permission fault

      195
    • 7.5.3 Alignment fault

      195
  • 7.6 MPU software-accessible registers

    196
• Level One Memory System

  197
  • 8.1 About the L1 memory system

    198
  • 8.2 About the error detection and correction schemes

    200
    • 8.2.1 Parity

      200
    • 8.2.2 Error checking and correction

      201
    • 8.2.3 Read-Modify-Write

      201
    • 8.2.4 Hard errors

      201
    • 8.2.5 Error correction

      202
  • 8.3 Fault handling

    203
    • 8.3.1 Faults

      203
    • 8.3.2 Fault status information

      205
    • 8.3.3 Correctable Fault Location Register

      206
    • 8.3.4 Usage models

      206
  • 8.4 About the TCMs

    209
    • 8.4.1 TCM attributes and permissions

      209
    • 8.4.2 ATCM and BTCM configuration

      210
    • 8.4.3 TCM internal error detection and correction

      210
    • 8.4.4 TCM arbitration

      211
    • 8.4.5 TCM initialization

      212
    • 8.4.6 TCM port protocol

      212
    • 8.4.7 External TCM errors

      212
    • 8.4.8 AXI slave interfaces for TCMs

      213
  • 8.5 About the caches

    214
    • 8.5.1 Store buffer

      214
    • 8.5.2 Cache maintenance operations

      215
    • 8.5.3 Cache error detection and correction

      216
    • 8.5.4 Cache RAM organization

      222
    • 8.5.5 Cache interaction with memory system

      227
  • 8.6 Internal exclusive monitor

    230
  • 8.7 Memory types and L1 memory system behavior

    231
  • 8.8 Error detection events

    232
    • 8.8.1 TCM error events

      232
    • 8.8.2 Instruction-cache error events

      232
    • 8.8.3 Data-cache error events

      232
    • 8.8.4 Events and the CFLR

      232
• Level Two Interface

  234
  • 9.1 About the L2 interface

    235
  • 9.2 AXI master interface

    236
    • 9.2.1 Identifiers for AXI bus accesses

      237
    • 9.2.2 Write response

      237
    • 9.2.3 Linefill buffers and the AXI master interface

      237
    • 9.2.4 Eviction buffer

      238
    • 9.2.5 Memory attributes

      238
  • 9.3 AXI master interface transfers

    240
    • 9.3.1 Restrictions on AXI transfers

      241
    • 9.3.2 Strongly Ordered and Device transactions

      241
    • 9.3.3 Linefills

      246
    • 9.3.4 Cache line write-back (eviction)

      246
    • 9.3.5 Non-cacheable reads

      246
    • 9.3.6 Non-cacheable or write-through writes

      248
    • 9.3.7 AXI transaction splitting

      249
    • 9.3.8 Normal write merging

      250
  • 9.4 AXI slave interface

    253
    • 9.4.1 AXI slave interface for cache RAMs

      253
    • 9.4.2 TCM parity and ECC support

      254
    • 9.4.3 External TCM errors

      254
    • 9.4.4 Cache parity and ECC support

      254
    • 9.4.5 AXI slave control

      254
    • 9.4.6 AXI slave characteristics

      255
  • 9.5 Enabling or disabling AXI slave accesses

    256
  • 9.6 Accessing RAMs using the AXI slave interface

    257
    • 9.6.1 TCM RAM access

      258
    • 9.6.2 Cache RAM access

      259
• Power Control

  266
  • 10.1 About power control

    267
  • 10.2 Power management

    268
    • 10.2.1 Run mode

      268
    • 10.2.2 Standby mode

      268
    • 10.2.3 Dormant mode

      268
    • 10.2.4 Shutdown mode

      268
    • 10.2.5 Communication to the Power Management Controller

      269
• Debug

  270
  • 11.1 Debug systems

    271
    • 11.1.1 Debug host

      271
    • 11.1.2 Protocol converter

      271
    • 11.1.3 Debug target

      271
  • 11.2 About the debug unit

    272
    • 11.2.1 Halting debug-mode debugging

      272
    • 11.2.2 Monitor debug-mode debugging

      272
    • 11.2.3 Programming the debug unit

      272
  • 11.3 Debug register interface

    274
    • 11.3.1 Coprocessor registers

      274
    • 11.3.2 CP14 access permissions

      274
    • 11.3.3 Coprocessor registers summary

      274
    • 11.3.4 Memory-mapped registers

      275
    • 11.3.5 Memory addresses for breakpoints and watchpoints

      276
    • 11.3.6 Power domains

      277
    • 11.3.7 Effects of resets on debug registers

      277
    • 11.3.8 APB port access permissions

      277
  • 11.4 Debug register descriptions

    279
    • 11.4.1 Accessing debug registers

      279
    • 11.4.2 CP14 c0, Debug ID Register

      279
    • 11.4.3 CP14 c0, Debug ROM Address Register

      281
    • 11.4.4 CP14 c0, Debug Self Address Offset Register

      281
    • 11.4.5 CP14 c1, Debug Status and Control Register

      283
    • 11.4.6 Data Transfer Register

      287
    • 11.4.7 Watchpoint Fault Address Register

      288
    • 11.4.8 Vector Catch Register

      288
    • 11.4.9 Debug State Cache Control Register

      290
    • 11.4.10 Instruction Transfer Register

      290
    • 11.4.11 Debug Run Control Register

      291
    • 11.4.12 Breakpoint Value Registers

      292
    • 11.4.13 Breakpoint Control Registers

      292
    • 11.4.14 Watchpoint Value Registers

      295
    • 11.4.15 Watchpoint Control Registers

      295
    • 11.4.16 Operating System Lock Status Register

      297
    • 11.4.17 Authentication Status Register

      298
    • 11.4.18 Device Power-down and Reset Control Register

      299
    • 11.4.19 Device Power-down and Reset Status Register

      299
  • 11.5 Management registers

    301
    • 11.5.1 Processor ID Registers

      301
    • 11.5.2 Claim Registers

      302
    • 11.5.3 Lock Access Register

      303
    • 11.5.4 Lock Status Register

      303
    • 11.5.5 Device Type Register

      304
    • 11.5.6 Debug Identification Registers

      304
  • 11.6 Debug events

    308
    • 11.6.1 Software debug event

      308
    • 11.6.2 Halting debug event

      309
    • 11.6.3 Behavior of the processor on debug events

      309
    • 11.6.4 Debug event priority

      309
    • 11.6.5 Watchpoint debug events

      309
  • 11.7 Debug exception

    310
    • 11.7.1 Effect of debug exceptions on CP15 registers and WFAR

      311
    • 11.7.2 Avoiding unrecoverable states

      312
  • 11.8 Debug state

    313
    • 11.8.1 Entering debug state

      313
    • 11.8.2 Behavior of the PC and CPSR in debug state

      314
    • 11.8.3 Executing instructions in debug state

      315
    • 11.8.4 Writing to the CPSR in debug state

      315
    • 11.8.5 Privilege

      315
    • 11.8.6 Accessing registers and memory

      315
    • 11.8.7 Coprocessor instructions

      316
    • 11.8.8 Effect of debug state on non-invasive debug

      316
    • 11.8.9 Effects of debug events on processor registers

      316
    • 11.8.10 Exceptions in debug state

      316
    • 11.8.11 Leaving debug state

      317
  • 11.9 Cache debug

    319
    • 11.9.1 Cache pollution in debug state

      319
    • 11.9.2 Cache coherency in debug state

      319
    • 11.9.3 Cache usage profiling

      319
  • 11.10 External debug interface

    320
    • 11.10.1 APB signals

      320
    • 11.10.2 Miscellaneous debug signals

      320
    • 11.10.3 Authentication signals

      321
  • 11.11 Using the debug functionality

    323
    • 11.11.1 Debug communications channel

      324
    • 11.11.2 Programming breakpoints and watchpoints

      326
    • 11.11.3 Single-stepping

      329
    • 11.11.4 Debug state entry

      330
    • 11.11.5 Debug state exit

      331
    • 11.11.6 Accessing registers and memory in debug state

      332
  • 11.12 Debugging systems with energy management capabilities

    340
    • 11.12.1 Emulating power down

      340
• FPU Programmer’s Model

  342
  • 12.1 About the FPU programmer’s model

    343
    • 12.1.1 FPU functionality

      343
    • 12.1.2 About the VFPv3-D16 architecture

      343
  • 12.2 General-purpose registers

    344
    • 12.2.1 FPU views of the register bank

      344
  • 12.3 System registers

    345
    • 12.3.1 Floating-Point System ID Register, FPSID

      346
    • 12.3.2 Floating-Point Status and Control Register, FPSCR

      347
    • 12.3.3 Floating-Point Exception Register, FPEXC

      348
    • 12.3.4 Media and VFP Feature Registers, MVFR0 and MVFR1

      349
  • 12.4 Modes of operation

    351
    • 12.4.1 Full-compliance mode

      351
    • 12.4.2 Flush-to-zero mode

      351
    • 12.4.3 Default NaN mode

      351
  • 12.5 Compliance with the IEEE 754 standard

    352
    • 12.5.1 Complete implementation of the IEEE 754 standard

      352
    • 12.5.2 IEEE 754 standard implementation choices

      352
    • 12.5.3 Exceptions

      354
• Integration Test Registers

  355
  • 13.1 About Integration Test Registers

    356
  • 13.2 Programming and reading Integration Test Registers

    357
    • 13.2.1 Software access using APB

      357
  • 13.3 Summary of the processor registers used for integration testing

    358
  • 13.4 Processor integration testing

    359
    • 13.4.1 Using the Integration Test Registers

      360
    • 13.4.2 Performing integration testing

      360
    • 13.4.3 ITETMIF Register (ETM interface)

      361
    • 13.4.4 ITMISCOUT Register (Miscellaneous Outputs)

      362
    • 13.4.5 ITMISCIN Register (Miscellaneous Inputs)

      362
    • 13.4.6 Integration Mode Control Register (ITCTRL)

      363
• Cycle Timings and Interlock Behavior

  365
  • 14.1 About cycle timings and interlock behavior

    367
    • 14.1.1 Instruction execution overview

      367
    • 14.1.2 Conditional instructions

      368
    • 14.1.3 Flag-setting instructions

      368
    • 14.1.4 Definition of terms

      368
    • 14.1.5 Assembler language syntax

      369
  • 14.2 Register interlock examples

    370
  • 14.3 Data processing instructions

    371
    • 14.3.1 Cycle counts if destination is not PC

      371
    • 14.3.2 Cycle counts if destination is the PC

      371
    • 14.3.3 Example interlocks

      372
  • 14.4 QADD, QDADD, QSUB, and QDSUB instructions

    373
  • 14.5 Media data-processing

    374
  • 14.6 Sum of Absolute Differences (SAD)

    375
    • 14.6.1 Example interlocks

      375
  • 14.7 Multiplies

    376
  • 14.8 Divide

    378
  • 14.9 Branches

    379
  • 14.10 Processor state updating instructions

    380
  • 14.11 Single load and store instructions

    381
    • 14.11.1 Base register update

      382
  • 14.12 Load and Store Double instructions

    384
  • 14.13 Load and Store Multiple instructions

    385
    • 14.13.1 Load and Store Multiples, other than load multiples including the PC

      385
    • 14.13.2 Load Multiples, where the PC is in the register list

      386
    • 14.13.3 Example Interlocks

      386
  • 14.14 RFE and SRS instructions

    388
  • 14.15 Synchronization instructions

    389
  • 14.16 Coprocessor instructions

    390
  • 14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions

    391
  • 14.18 Miscellaneous instructions

    392
  • 14.19 Floating-point register transfer instructions

    393
  • 14.20 Floating-point load/store instructions

    394
  • 14.21 Floating-point single-precision data processing instructions

    396
  • 14.22 Floating-point double-precision data processing instructions

    397
  • 14.23 Dual issue

    398
    • 14.23.1 Dual issue rules

      398
    • 14.23.2 Permitted combinations

      399
• AC Characteristics

  401
  • 15.1 Processor timing

    402
  • 15.2 Processor timing parameters

    403
    • 15.2.1 Input port timing parameters

      403
    • 15.2.2 Output ports timing parameters

      408
• Processor Signal Descriptions

  414
  • A.1 About the processor signal descriptions

    415
  • A.2 Global signals

    416
  • A.3 Configuration signals

    417
  • A.4 Interrupt signals, including VIC interface signals

    420
  • A.5 L2 interface signals

    421
    • A.5.1 AXI master port

      421
    • A.5.2 AXI master port error detection signals

      423
    • A.5.3 AXI slave port

      423
    • A.5.4 AXI slave port error detection signals

      425
  • A.6 TCM interface signals

    426
  • A.7 Dual core interface signals

    429
  • A.8 Debug interface signals

    430
  • A.9 ETM interface signals

    432
  • A.10 Test signals

    433
  • A.11 MBIST signals

    434
  • A.12 Validation signals

    435
  • A.13 FPU signals

    436
• ECC Schemes

  437
  • B.1 ECC scheme selection guidelines

    438
• Revisions

  439
• Glossary

  442