ARM R4F Manuale Utente

ARM DDI 0363E

14-5

ID013010

The syntax used throughout this chapter is unified assembler and the timings apply to ARM and 
Thumb instructions.

Early Reg

The specified registers are required at the start of the Ex1 stage. Add one cycle to the Result Latency 
of the instruction producing this register.

Very Early Reg

The specified registers are required at the start of the Iss stage. Add two cycles to the Result Latency 
of the instruction producing this register, or one cycle if the instruction producing this register is an 

LDM

, 

LDR

, 

LDRD

, 

LDREX

, or 

LDRT

. The lower Result Latency does not apply if this register is the base register of 

the load instruction producing this register, or if the load instruction is an 

LDRB

, 

LDRBT

, 

LDRH

, 

LDRSB

, or 

LDRSH

.

Interlock

There is a data dependency between two instructions in the pipeline, resulting in the Iss stage being 
stalled until the processor resolves the dependency.